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fix(cpu): Ensure mask the high bits of the flag register 

There was a bug where POP AF returned 0x1301. In this example, the A
register would be set to 0x13, and the Flag register woud be set to
0x01, which is an invalid state considering only bits 4 -> 7 of the flag
register are used. This commit masks the flag register with & 0xF0
whenever it is read or written to so that we can ensure that only the
high bits can ever be potentially set
This commit is contained in:
Rekai Nyangadzayi Musuka 2021-03-26 20:25:30 -05:00
parent 15781b3d5a
commit 2bf877d1ec
1 changed files with 2 additions and 2 deletions
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4
src/cpu.rs
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@ -441,13 +441,13 @@ impl Display for Flags {
impl From<Flags> for u8 { impl From<Flags> for u8 {
fn from(flags: Flags) -> Self { fn from(flags: Flags) -> Self {
flags.0 flags.0 & 0xF0
} }
} }
impl From<u8> for Flags { impl From<u8> for Flags {
fn from(byte: u8) -> Self { fn from(byte: u8) -> Self {
Self(byte) Self(byte & 0xF0)
} }
} }