feat: stub 0xff0f and 0xffff from interrupt
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parent
e693ad8a3c
commit
1b53363095
10
src/bus.rs
10
src/bus.rs
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@ -1,7 +1,9 @@
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use super::cartridge::Cartridge;
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use super::cartridge::Cartridge;
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use super::interrupt::Interrupt;
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use super::ppu::PPU;
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use super::ppu::PPU;
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use super::timer::Timer;
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use super::timer::Timer;
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use super::work_ram::{VariableWorkRAM, WorkRAM};
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use super::work_ram::{VariableWorkRAM, WorkRAM};
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#[derive(Debug, Clone)]
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#[derive(Debug, Clone)]
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pub struct Bus {
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pub struct Bus {
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boot: Option<[u8; 256]>, // Boot ROM is 256b long
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boot: Option<[u8; 256]>, // Boot ROM is 256b long
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@ -10,6 +12,7 @@ pub struct Bus {
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wram: WorkRAM,
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wram: WorkRAM,
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vwram: VariableWorkRAM,
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vwram: VariableWorkRAM,
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timer: Timer,
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timer: Timer,
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interrupt: Interrupt,
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}
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}
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impl Default for Bus {
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impl Default for Bus {
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@ -21,6 +24,7 @@ impl Default for Bus {
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wram: Default::default(),
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wram: Default::default(),
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vwram: Default::default(),
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vwram: Default::default(),
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timer: Default::default(),
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timer: Default::default(),
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interrupt: Default::default(),
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}
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}
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}
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}
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}
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}
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@ -91,6 +95,7 @@ impl Bus {
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// IO Registers
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// IO Registers
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match addr {
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match addr {
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0xFF07 => self.timer.control.into(),
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0xFF07 => self.timer.control.into(),
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0xFF0F => self.interrupt.flag.into(),
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_ => unimplemented!("Unable to read {:#06X} in I/O Registers", addr),
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_ => unimplemented!("Unable to read {:#06X} in I/O Registers", addr),
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}
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}
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}
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}
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@ -100,7 +105,7 @@ impl Bus {
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}
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}
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0xFFFF => {
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0xFFFF => {
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// Interupts Enable Register
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// Interupts Enable Register
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unimplemented!("Unable to read IE Register {:#06X} ", addr);
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self.interrupt.enable.into()
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}
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}
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}
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}
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}
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}
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@ -147,6 +152,7 @@ impl Bus {
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// IO Registers
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// IO Registers
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match addr {
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match addr {
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0xFF07 => self.timer.control = byte.into(),
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0xFF07 => self.timer.control = byte.into(),
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0xFF0F => self.interrupt.flag = byte.into(),
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_ => unimplemented!("Unable to write to {:#06X} in I/O Registers", addr),
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_ => unimplemented!("Unable to write to {:#06X} in I/O Registers", addr),
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};
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};
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}
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}
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@ -156,7 +162,7 @@ impl Bus {
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}
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}
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0xFFFF => {
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0xFFFF => {
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// Interupts Enable Register
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// Interupts Enable Register
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unimplemented!("Unable to write to IE Register {:#06X} ", addr);
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self.interrupt.enable = byte.into();
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}
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}
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}
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}
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}
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}
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@ -0,0 +1,74 @@
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#[derive(Debug, Clone, Copy, Default)]
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pub struct Interrupt {
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pub flag: InterruptFlag,
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pub enable: InterruptEnable,
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}
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#[derive(Debug, Clone, Copy, Default)]
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pub struct InterruptEnable {
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vblank: bool,
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lcd_stat: bool,
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timer: bool,
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serial: bool,
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joypad: bool,
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}
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impl From<u8> for InterruptEnable {
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fn from(byte: u8) -> Self {
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Self {
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vblank: (byte >> 0 & 0x01) == 0x01,
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lcd_stat: (byte >> 1 & 0x01) == 0x01,
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timer: (byte >> 2 & 0x01) == 0x01,
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serial: (byte >> 3 & 0x01) == 0x01,
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joypad: (byte >> 4 & 0x01) == 0x01,
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}
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}
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}
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impl From<InterruptEnable> for u8 {
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fn from(flag: InterruptEnable) -> Self {
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(flag.joypad as u8) << 4
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| (flag.serial as u8) << 3
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| (flag.timer as u8) << 2
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| (flag.lcd_stat as u8) << 1
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| (flag.vblank as u8) << 0
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}
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}
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#[derive(Debug, Clone, Copy, Default)]
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pub struct InterruptFlag {
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vblank: bool,
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lcd_stat: bool,
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timer: bool,
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serial: bool,
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joypad: bool,
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}
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impl From<u8> for InterruptFlag {
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fn from(byte: u8) -> Self {
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Self {
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vblank: (byte >> 0 & 0x01) == 0x01,
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lcd_stat: (byte >> 1 & 0x01) == 0x01,
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timer: (byte >> 2 & 0x01) == 0x01,
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serial: (byte >> 3 & 0x01) == 0x01,
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joypad: (byte >> 4 & 0x01) == 0x01,
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}
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}
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}
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impl From<InterruptFlag> for u8 {
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fn from(flag: InterruptFlag) -> Self {
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(flag.joypad as u8) << 4
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| (flag.serial as u8) << 3
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| (flag.timer as u8) << 2
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| (flag.lcd_stat as u8) << 1
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| (flag.vblank as u8) << 0
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}
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}
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enum InterruptType {
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VBlank,
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LCDStat,
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Timer,
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Serial,
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Joypad,
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}
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@ -2,6 +2,7 @@ mod bus;
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mod cartridge;
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mod cartridge;
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pub mod cpu;
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pub mod cpu;
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mod instruction;
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mod instruction;
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mod interrupt;
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mod ppu;
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mod ppu;
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mod timer;
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mod timer;
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mod work_ram;
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mod work_ram;
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