chore: add debug information to bus.rs
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parent
4d2e0e33f2
commit
1502cc3ec2
36
src/bus.rs
36
src/bus.rs
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@ -1,34 +1,48 @@
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const ROM: &[u8; 256] = include_bytes!("../bin/DMG_ROM.bin");
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#[derive(Debug, Copy, Clone)]
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pub struct Bus {
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boot: [u8; 256],
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}
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#[derive(Debug, Copy, Clone, Default)]
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impl Default for Bus {
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pub struct Bus {}
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fn default() -> Self {
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Self {
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boot: include_bytes!("../bin/DMG_ROM.bin").to_owned(),
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}
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}
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}
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impl Bus {
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impl Bus {
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pub fn read_byte(&self, addr: u16) -> u8 {
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pub fn read_byte(&self, addr: u16) -> u8 {
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match addr {
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match addr {
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0x0000..=0x00FF => {
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0x0000..=0x00FF => {
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// Restart and Interrupt Vectors
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// Restart and Interrupt Vectors
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ROM[addr as usize]
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self.boot[addr as usize]
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}
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}
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_ => unimplemented!(),
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_ => unimplemented!("Can't read byte from {:#06x}", addr),
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}
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}
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}
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}
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pub fn write_byte(&mut self, _addr: u16, _byte: u8) {
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pub fn write_byte(&mut self, addr: u16, byte: u8) {
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unimplemented!()
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match addr {
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0x000..=0x0FF => {
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// Restart and Itterupt Vectors
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self.boot[addr as usize] = byte;
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}
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_ => unimplemented!("Can't write {:#04x} to {:#06x}", byte, addr),
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}
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}
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}
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pub fn read_word(&self, addr: u16) -> u16 {
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pub fn read_word(&self, addr: u16) -> u16 {
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match addr {
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match addr {
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0x0000..=0x00FF => {
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0x0000..=0x00FF => {
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// Restart and Interrupt Vectors
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// Restart and Interrupt Vectors
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(ROM[(addr + 1) as usize] as u16) << 8 | ROM[addr as usize] as u16
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(self.boot[(addr + 1) as usize] as u16) << 8 | self.boot[addr as usize] as u16
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}
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}
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_ => unimplemented!(),
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_ => unimplemented!("Can't read word from {:#06x}", addr),
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}
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}
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}
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}
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pub fn write_word(&mut self, _addr: u16, _word: u16) {
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pub fn write_word(&mut self, addr: u16, word: u16) {
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unimplemented!()
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unimplemented!("Can't write {:#06x} to {:#06x}", word, addr)
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}
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}
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}
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}
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