paoda
/
gb
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Implement decode for all x=0 unprefixed opcodes.

This commit is contained in:
Rekai Nyangadzayi Musuka 2020-08-23 23:56:20 -05:00
parent f97bf9dbb7
commit 146e2dc066
1 changed files with 79 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

79
src/instruction.rs
View File

@ -9,6 +9,24 @@ pub enum Instruction {
JP(Condition, Argument),
JR(Condition, i8),
ADD(Argument, Argument),
LDD(Argument, Argument),
LDI(Argument, Argument),
INC(AllRegisters),
DEC(AllRegisters),
RLCA,
RRCA,
RLA,
RRA,
DAA,
CPL,
SCF,
CCF,
}
pub enum AllRegisters {
U8(Register),
U16(RegisterPair),
IndirectHL,
}
pub enum Argument {
@ -63,21 +81,68 @@ impl Instruction {
)
}
(0, 2, 0, _, 0) => Instruction::LD(
// LD (BC), A
Argument::IndirectRegister(RegisterPair::BC),
Argument::Register(Register::A),
),
(0, 2, 0, _, 1) => Instruction::LD(
// LD (DE), A
Argument::IndirectRegister(RegisterPair::DE),
Argument::Register(Register::A),
),
(0, 2, 1, _, 0) => Instruction::LD(
// LD A, (BC)
Argument::Register(Register::A),
Argument::IndirectRegister(RegisterPair::BC),
),
(0, 2, 1, _, 1) => Instruction::LD(
// LD A, (DE)
Argument::Register(Register::A),
Argument::IndirectRegister(RegisterPair::DE),
),
(0, 2, 0, _, 2) => Instruction::LDI(
// LD (HL+), A
Argument::IndirectRegister(RegisterPair::HL),
Argument::Register(Register::A),
),
(0, 2, 0, _, 3) => Instruction::LDD(
// LD (HL-), A
Argument::IndirectRegister(RegisterPair::HL),
Argument::Register(Register::A),
),
(0, 2, 1, _, 2) => Instruction::LDI(
// LD A, (HL+)
Argument::Register(Register::A),
Argument::IndirectRegister(RegisterPair::HL),
),
(0, 2, 1, _, 3) => Instruction::LDD(
// LD A, (HL-)
Argument::Register(Register::A),
Argument::IndirectRegister(RegisterPair::HL),
),
(0, 3, 0, _, p) => Instruction::INC(AllRegisters::U16(Self::table_rp(p))), // INC rp[p]
(0, 3, 1, _, p) => Instruction::DEC(AllRegisters::U16(Self::table_rp(p))), // DEC rp[p]
(0, 4, _, y, _) => Instruction::INC(Self::table_r(y)), // INC r[y]
(0, 5, _, y, _) => Instruction::DEC(Self::table_r(y)), // DEC r[y]
(0, 6, _, y, _) => Instruction::LD(
// LD r[y], n
{
match Self::table_r(y) {
AllRegisters::U8(reg) => Argument::Register(reg),
AllRegisters::IndirectHL => Argument::IndirectRegister(RegisterPair::HL),
_ => unreachable!(),
}
},
Argument::ImmediateByte(n),
),
(0, 7, _, 0, _) => Instruction::RLCA,
(0, 7, _, 1, _) => Instruction::RRCA,
(0, 7, _, 2, _) => Instruction::RLA,
(0, 7, _, 3, _) => Instruction::RRA,
(0, 7, _, 4, _) => Instruction::DAA,
(0, 7, _, 5, _) => Instruction::CPL,
(0, 7, _, 6, _) => Instruction::SCF,
(0, 7, _, 7, _) => Instruction::CCF,
_ => unreachable!(),
}
}
@ -86,6 +151,20 @@ impl Instruction {
unimplemented!()
}
fn table_r(index: u8) -> AllRegisters {
match index {
0 => AllRegisters::U8(Register::B),
1 => AllRegisters::U8(Register::C),
2 => AllRegisters::U8(Register::D),
3 => AllRegisters::U8(Register::E),
4 => AllRegisters::U8(Register::H),
5 => AllRegisters::U8(Register::L),
6 => AllRegisters::IndirectHL,
7 => AllRegisters::U8(Register::A),
_ => unreachable!(),
}
}
fn table_rp2(index: u8) -> RegisterPair {
match index {
0 => RegisterPair::BC,