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fix: squash bug in 64 LD instructions

This commit is contained in:
Rekai Nyangadzayi Musuka 2021-01-17 17:31:45 -06:00
parent 834423fe18
commit 072c5f1b70
1 changed files with 33 additions and 4 deletions
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33
src/instruction.rs
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@ -233,11 +233,40 @@ impl Instruction {
(LDTarget::Register(lhs), LDTarget::Register(rhs)) => { (LDTarget::Register(lhs), LDTarget::Register(rhs)) => {
// LD r[y], r[z] | Store value of RHS Register in LHS Register // LD r[y], r[z] | Store value of RHS Register in LHS Register
// FIXME: panicking is the right thing to do, but maybe .unwrap is too unclear? let rhs_value = {
let rhs_value = cpu.register(Register::try_from(rhs).unwrap()); match rhs {
InstrRegister::B
| InstrRegister::C
| InstrRegister::D
| InstrRegister::E
| InstrRegister::H
| InstrRegister::L
| InstrRegister::A => cpu.register(Register::try_from(rhs).unwrap()),
InstrRegister::IndirectHL => {
let addr = cpu.register_pair(RegisterPair::HL);
cpu.read_byte(addr)
}
}
};
match lhs {
InstrRegister::B
| InstrRegister::C
| InstrRegister::D
| InstrRegister::E
| InstrRegister::H
| InstrRegister::L
| InstrRegister::A => {
cpu.set_register(Register::try_from(lhs).unwrap(), rhs_value); cpu.set_register(Register::try_from(lhs).unwrap(), rhs_value);
Cycles(4) Cycles(4)
} }
InstrRegister::IndirectHL => {
let addr = cpu.register_pair(RegisterPair::HL);
cpu.write_byte(addr, rhs_value);
Cycles(8)
}
}
}
(LDTarget::ByteAtAddressWithOffset(n), LDTarget::Register(InstrRegister::A)) => { (LDTarget::ByteAtAddressWithOffset(n), LDTarget::Register(InstrRegister::A)) => {
// LD (0xFF00 + n), A | Store register A at address (0xFF00 + n) // LD (0xFF00 + n), A | Store register A at address (0xFF00 + n)
cpu.write_byte(0xFF00 + (n as u16), cpu.register(Register::A)); cpu.write_byte(0xFF00 + (n as u16), cpu.register(Register::A));