Restart Project
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@@ -1,262 +0,0 @@
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use super::cpu::Cpu;
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use super::cpu::Register;
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use super::cpu::RegisterPair;
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pub enum Instruction {
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NOP,
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LD(Argument, Argument),
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STOP,
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JP(Condition, Argument),
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JR(Condition, i8),
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ADD(Argument, Argument),
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LDD(Argument, Argument),
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LDI(Argument, Argument),
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INC(AllRegisters),
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DEC(AllRegisters),
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RLCA,
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RRCA,
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RLA,
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RRA,
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DAA,
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CPL,
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SCF,
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CCF,
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HALT,
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ADC(Argument, Argument),
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SUB,
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SBC(Argument, Argument),
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AND,
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XOR,
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OR,
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CP,
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RET(Condition),
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}
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pub enum AllRegisters {
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U8(Register),
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U16(RegisterPair),
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IndirectHL,
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}
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pub enum Argument {
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ImmediateByte(u8),
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ImmediateWord(u16),
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IndirectImmediateByte(u16),
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Register(Register),
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RegisterPair(RegisterPair),
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IndirectRegister(RegisterPair),
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}
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impl Instruction {
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pub fn from_byte(cpu: &Cpu, byte: u8) -> Instruction {
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if byte == 0xCB {
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Self::from_prefixed_byte(cpu, byte)
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} else {
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Self::from_unprefixed_byte(cpu, byte)
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}
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}
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pub fn from_unprefixed_byte(cpu: &Cpu, byte: u8) -> Instruction {
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// https://gb-archive.github.io/salvage/decoding_gbz80_opcodes/Decoding%20Gamboy%20Z80%20Opcodes.html
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let x = (byte >> 6) & 0b00000011;
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let y = (byte >> 3) & 0b00000111;
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let z = byte & 0b00000111;
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let p = y >> 1;
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let q = y >> 3 & 0b00000001;
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let n = cpu.read_byte(cpu.register_pair(RegisterPair::PC) + 1);
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let nn = cpu.read_word(cpu.register_pair(RegisterPair::PC) + 1);
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match (x, z, q, y, p) {
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(0, 0, _, 0, _) => Instruction::NOP, // NOP
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(0, 0, _, 1, _) => Instruction::LD(
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// LD (nn), SP
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Argument::IndirectImmediateByte(nn),
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Argument::RegisterPair(RegisterPair::SP),
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),
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(0, 0, _, 2, _) => Instruction::STOP, // STOP
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(0, 0, _, 3, _) => Instruction::JR(Condition::Always, n as i8), // JR d
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(0, 0, _, 4..=7, _) => Instruction::JR(Self::table_cc(y - 4), n as i8), // JR cc[y - 4], d
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(0, 1, 0, _, p) => Instruction::LD(
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// LD rp[p], nn
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Argument::RegisterPair(Self::table_rp(p)),
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Argument::IndirectImmediateByte(nn),
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),
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(0, 1, 1, _, p) => {
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// ADD HL, rp[p]
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Instruction::ADD(
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Argument::RegisterPair(RegisterPair::HL),
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Argument::RegisterPair(Self::table_rp(p)),
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)
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}
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(0, 2, 0, _, 0) => Instruction::LD(
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// LD (BC), A
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Argument::IndirectRegister(RegisterPair::BC),
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Argument::Register(Register::A),
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),
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(0, 2, 0, _, 1) => Instruction::LD(
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// LD (DE), A
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Argument::IndirectRegister(RegisterPair::DE),
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Argument::Register(Register::A),
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),
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(0, 2, 1, _, 0) => Instruction::LD(
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// LD A, (BC)
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Argument::Register(Register::A),
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Argument::IndirectRegister(RegisterPair::BC),
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),
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(0, 2, 1, _, 1) => Instruction::LD(
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// LD A, (DE)
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Argument::Register(Register::A),
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Argument::IndirectRegister(RegisterPair::DE),
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),
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(0, 2, 0, _, 2) => Instruction::LDI(
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// LD (HL+), A
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Argument::IndirectRegister(RegisterPair::HL),
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Argument::Register(Register::A),
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),
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(0, 2, 0, _, 3) => Instruction::LDD(
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// LD (HL-), A
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Argument::IndirectRegister(RegisterPair::HL),
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Argument::Register(Register::A),
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),
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(0, 2, 1, _, 2) => Instruction::LDI(
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// LD A, (HL+)
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Argument::Register(Register::A),
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Argument::IndirectRegister(RegisterPair::HL),
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),
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(0, 2, 1, _, 3) => Instruction::LDD(
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// LD A, (HL-)
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Argument::Register(Register::A),
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Argument::IndirectRegister(RegisterPair::HL),
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),
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(0, 3, 0, _, p) => Instruction::INC(AllRegisters::U16(Self::table_rp(p))), // INC rp[p]
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(0, 3, 1, _, p) => Instruction::DEC(AllRegisters::U16(Self::table_rp(p))), // DEC rp[p]
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(0, 4, _, y, _) => Instruction::INC(Self::table_r(y)), // INC r[y]
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(0, 5, _, y, _) => Instruction::DEC(Self::table_r(y)), // DEC r[y]
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(0, 6, _, y, _) => Instruction::LD(
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// LD r[y], n
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Self::arg_table_r(y),
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Argument::ImmediateByte(n),
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),
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(0, 7, _, 0, _) => Instruction::RLCA,
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(0, 7, _, 1, _) => Instruction::RRCA,
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(0, 7, _, 2, _) => Instruction::RLA,
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(0, 7, _, 3, _) => Instruction::RRA,
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(0, 7, _, 4, _) => Instruction::DAA,
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(0, 7, _, 5, _) => Instruction::CPL,
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(0, 7, _, 6, _) => Instruction::SCF,
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(0, 7, _, 7, _) => Instruction::CCF,
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(1, 6, _, 6, _) => Instruction::HALT,
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(1, z, _, y, _) => Instruction::LD(
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// LD r[y], r[z]
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Self::arg_table_r(y),
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Self::arg_table_r(z),
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),
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(2, z, _, y, _) => Self::table_alu(y, z),
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(3, 0, _, 0..=3, _) => Instruction::RET(
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// RET cc[y]
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Self::table_cc(y),
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),
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(3, 0, _, 4, _) => Instruction::LD(
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// LD (0xFF00 + n), A
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Argument::IndirectImmediateByte(0xFF00 + (n as u16)),
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Argument::Register(Register::A),
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),
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(3, 0, _, 5, _) => Instruction::ADD(
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Argument::RegisterPair(RegisterPair::SP),
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Argument::ImmediateByte(n),
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),
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_ => unreachable!(),
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}
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}
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pub fn from_prefixed_byte(cpu: &Cpu, byte: u8) -> Instruction {
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unimplemented!()
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}
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fn arg_table_r(index: u8) -> Argument {
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match Self::table_r(index) {
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AllRegisters::U8(register) => Argument::Register(register),
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AllRegisters::IndirectHL => Argument::IndirectRegister(RegisterPair::HL),
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_ => unreachable!(),
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}
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}
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fn table_r(index: u8) -> AllRegisters {
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match index {
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0 => AllRegisters::U8(Register::B),
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1 => AllRegisters::U8(Register::C),
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2 => AllRegisters::U8(Register::D),
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3 => AllRegisters::U8(Register::E),
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4 => AllRegisters::U8(Register::H),
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5 => AllRegisters::U8(Register::L),
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6 => AllRegisters::IndirectHL,
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7 => AllRegisters::U8(Register::A),
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_ => unreachable!(),
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}
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}
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fn table_rp2(index: u8) -> RegisterPair {
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match index {
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0 => RegisterPair::BC,
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1 => RegisterPair::DE,
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2 => RegisterPair::HL,
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3 => RegisterPair::AF,
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_ => unreachable!(),
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}
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}
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fn table_rp(index: u8) -> RegisterPair {
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match index {
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0 => RegisterPair::BC,
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1 => RegisterPair::DE,
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2 => RegisterPair::HL,
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3 => RegisterPair::SP,
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_ => unreachable!(),
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}
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}
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fn table_cc(index: u8) -> Condition {
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match index {
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0 => Condition::NotZero,
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1 => Condition::Zero,
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2 => Condition::NotCarry,
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3 => Condition::Carry,
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_ => unreachable!(),
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}
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}
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fn table_alu(fn_index: u8, reg_index: u8) -> Instruction {
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match fn_index {
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0 => Instruction::ADD(
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// ADD A, r[z]
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Argument::Register(Register::A),
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Self::arg_table_r(reg_index),
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),
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1 => Instruction::ADC(
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// ADC A, r[z]
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Argument::Register(Register::A),
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Self::arg_table_r(reg_index),
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),
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2 => Instruction::SUB,
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3 => Instruction::SBC(
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// SBC A, r[z]
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Argument::Register(Register::A),
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Self::arg_table_r(reg_index),
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),
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4 => Instruction::AND,
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5 => Instruction::XOR,
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6 => Instruction::OR,
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7 => Instruction::CP,
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_ => unreachable!(),
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}
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}
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}
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pub enum Condition {
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NotZero,
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Zero,
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NotCarry,
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Carry,
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Always,
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}
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