2020-12-24 06:27:06 +00:00
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use super::cartridge::Cartridge;
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2021-01-18 03:13:59 +00:00
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use super::high_ram::HighRAM;
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2021-01-19 07:36:44 +00:00
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use super::instruction::Cycles;
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2021-01-03 07:38:31 +00:00
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use super::interrupt::Interrupt;
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2020-12-24 06:27:06 +00:00
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use super::ppu::PPU;
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2021-01-19 07:36:44 +00:00
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use super::serial::Serial;
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2021-01-03 08:05:46 +00:00
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use super::sound::Sound;
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2021-01-03 07:21:19 +00:00
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use super::timer::Timer;
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2021-01-03 06:28:07 +00:00
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use super::work_ram::{VariableWorkRAM, WorkRAM};
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2021-01-03 07:38:31 +00:00
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2020-12-24 01:39:37 +00:00
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#[derive(Debug, Clone)]
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2020-12-23 09:43:49 +00:00
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pub struct Bus {
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2020-12-24 03:24:27 +00:00
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boot: Option<[u8; 256]>, // Boot ROM is 256b long
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2020-12-24 01:39:37 +00:00
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cartridge: Option<Cartridge>,
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2021-01-19 02:47:09 +00:00
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pub ppu: PPU,
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2021-01-03 06:28:07 +00:00
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wram: WorkRAM,
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vwram: VariableWorkRAM,
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timer: Timer,
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interrupt: Interrupt,
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sound: Sound,
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2021-01-18 03:13:59 +00:00
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hram: HighRAM,
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serial: Serial,
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2020-12-23 09:43:49 +00:00
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}
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2020-12-23 09:25:16 +00:00
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2020-12-23 09:43:49 +00:00
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impl Default for Bus {
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fn default() -> Self {
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Self {
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boot: None,
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2020-12-24 01:39:37 +00:00
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cartridge: None,
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2020-12-24 06:27:06 +00:00
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ppu: Default::default(),
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wram: Default::default(),
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vwram: Default::default(),
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2021-01-03 07:21:19 +00:00
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timer: Default::default(),
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2021-01-03 07:38:31 +00:00
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interrupt: Default::default(),
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2021-01-03 08:05:46 +00:00
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sound: Default::default(),
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2021-01-18 03:13:59 +00:00
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hram: Default::default(),
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2021-01-19 07:36:44 +00:00
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serial: Default::default(),
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2020-12-24 01:39:37 +00:00
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}
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}
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}
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impl Bus {
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pub fn with_boot() -> Self {
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Self {
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boot: Some(include_bytes!("../bin/DMG_ROM.bin").to_owned()),
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2020-12-24 03:24:27 +00:00
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..Default::default()
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2020-12-23 09:43:49 +00:00
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}
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}
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2020-12-24 01:39:37 +00:00
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pub fn load_cartridge(&mut self, path: &str) {
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self.cartridge = Some(Cartridge::new(path).unwrap());
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}
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2021-01-19 04:54:38 +00:00
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pub fn step(&mut self, cycles: Cycles) {
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let _ = self.timer.step(cycles);
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let _ = self.sound.step(cycles);
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let _ = self.ppu.step(cycles);
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}
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2020-12-23 09:43:49 +00:00
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}
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2020-08-29 23:38:27 +00:00
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impl Bus {
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2020-09-04 05:41:19 +00:00
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pub fn read_byte(&self, addr: u16) -> u8 {
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match addr {
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2020-12-24 01:39:37 +00:00
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0x0000..=0x3FFF => {
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// 16KB ROM bank 00
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if addr <= 0x00FF && self.boot.is_some() {
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let boot = self.boot.unwrap();
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boot[addr as usize]
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} else {
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match &self.cartridge {
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Some(cart) => cart.read_byte(addr),
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None => panic!("Tried to read from a non-existant cartridge"),
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}
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}
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}
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0x4000..=0x7FFF => match &self.cartridge {
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// 16KB ROM Bank 01 -> NN (switchable via MB)
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Some(cart) => cart.read_byte(addr),
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None => panic!("Tried to read from a non-existant cartridge"),
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},
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0x8000..=0x9FFF => {
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// 8KB Video RAM
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self.ppu.vram[(addr - 0x8000) as usize]
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}
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0xA000..=0xBFFF => match &self.cartridge {
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// 8KB External RAM
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Some(cart) => cart.read_byte(addr),
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None => panic!("Tried to read from the external RAM of a non-existant cartridge"),
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},
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0xC000..=0xCFFF => {
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// 4KB Work RAM Bank 0
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self.wram.read_byte((addr - 0xC000) as usize)
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}
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0xD000..=0xDFFF => {
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// 4KB Work RAM Bank 1 -> N
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self.vwram.read_byte((addr - 0xD000) as usize)
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}
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0xE000..=0xFDFF => {
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// Mirror of 0xC000 to 0xDDFF
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unimplemented!("Unable to read {:#06X} in Restricted Mirror", addr);
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}
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0xFE00..=0xFE9F => {
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// Sprite Attrbute Table
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unimplemented!("Unable to read {:#06X} in the Sprite Attribute Table", addr);
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}
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0xFEA0..=0xFEFF => unimplemented!("{:#06X} is not allowed to be used", addr),
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0xFF00..=0xFF7F => {
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// IO Registers
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match addr {
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0xFF01 => self.serial.next,
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0xFF02 => self.serial.control.into(),
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0xFF07 => self.timer.control.into(),
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0xFF0F => self.interrupt.flag.into(),
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0xFF11 => self.sound.ch1.sound_duty.into(),
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0xFF12 => self.sound.ch1.vol_envelope.into(),
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0xFF14 => self.sound.ch1.freq.get_hi(),
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0xFF24 => self.sound.control.channel.into(),
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0xFF25 => self.sound.control.select.into(),
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0xFF26 => self.sound.control.status.into(),
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0xFF40 => self.ppu.lcd_control.into(),
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0xFF41 => self.ppu.stat.into(),
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0xFF42 => self.ppu.pos.scroll_y,
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0xFF43 => self.ppu.pos.scroll_x,
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0xFF44 => self.ppu.pos.line_y,
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0xFF47 => self.ppu.monochrome.bg_palette.into(),
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_ => unimplemented!("Unable to read {:#06X} in I/O Registers", addr),
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}
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2020-12-24 01:39:37 +00:00
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}
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0xFF80..=0xFFFE => {
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// High RAM
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self.hram.read_byte((addr - 0xFF80) as usize)
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2020-12-24 01:39:37 +00:00
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}
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0xFFFF => {
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// Interupts Enable Register
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self.interrupt.enable.into()
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2020-12-23 09:25:16 +00:00
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}
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}
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2020-08-29 23:38:27 +00:00
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}
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2020-12-23 09:43:49 +00:00
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pub fn write_byte(&mut self, addr: u16, byte: u8) {
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match addr {
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0x0000..=0x3FFF => {
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// 16KB ROM bank 00
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2021-01-20 07:39:24 +00:00
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match self.cartridge.as_mut() {
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Some(cart) => cart.write_byte(addr, byte),
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None => panic!("Tried to write into non-existent Cartridge"),
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}
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2020-12-24 03:24:27 +00:00
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}
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0x4000..=0x7FFF => {
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// 16KB ROM Bank 01 -> NN (switchable via MB)
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2021-01-20 07:39:24 +00:00
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match self.cartridge.as_mut() {
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Some(cart) => cart.write_byte(addr, byte),
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None => panic!("Tried to write into non-existent Cartridge"),
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}
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2020-12-24 03:24:27 +00:00
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}
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0x8000..=0x9FFF => {
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// 8KB Video RAM
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2020-12-24 06:27:06 +00:00
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self.ppu.vram[(addr - 0x8000) as usize] = byte;
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2020-12-24 03:24:27 +00:00
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}
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0xA000..=0xBFFF => {
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// 8KB External RAM
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2021-01-20 07:39:24 +00:00
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match self.cartridge.as_mut() {
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Some(cart) => cart.write_byte(addr, byte),
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None => panic!("Tried to write into non-existent Cartridge"),
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}
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2020-12-24 03:24:27 +00:00
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}
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0xC000..=0xCFFF => {
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// 4KB Work RAM Bank 0
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2021-01-03 06:28:07 +00:00
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self.wram.write_byte((addr - 0xC000) as usize, byte);
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2020-12-24 03:24:27 +00:00
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}
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0xD000..=0xDFFF => {
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// 4KB Work RAM Bank 1 -> N
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2021-01-03 06:28:07 +00:00
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self.vwram.write_byte((addr - 0xD000) as usize, byte);
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2020-12-24 03:24:27 +00:00
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}
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0xE000..=0xFDFF => {
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// Mirror of 0xC000 to 0xDDFF
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unimplemented!("Unable to write to {:#06X} in Restricted Mirror", addr);
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}
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0xFE00..=0xFE9F => {
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// Sprite Attrbute Table
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unimplemented!(
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"Unable to write to {:#06X} in the Sprite Attribute Table",
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addr
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);
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}
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0xFEA0..=0xFEFF => unimplemented!("{:#06X} is not allowed to be used", addr),
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0xFF00..=0xFF7F => {
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// IO Registers
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2021-01-03 07:21:19 +00:00
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match addr {
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0xFF01 => self.serial.next = byte,
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0xFF02 => self.serial.control = byte.into(),
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2021-01-03 07:21:19 +00:00
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0xFF07 => self.timer.control = byte.into(),
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2021-01-03 07:38:31 +00:00
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0xFF0F => self.interrupt.flag = byte.into(),
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2021-01-17 23:33:12 +00:00
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0xFF11 => self.sound.ch1.sound_duty = byte.into(),
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0xFF12 => self.sound.ch1.vol_envelope = byte.into(),
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2021-01-19 06:30:10 +00:00
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0xFF13 => self.sound.ch1.freq.set_lo(byte),
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0xFF14 => self.sound.ch1.freq.set_hi(byte),
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2021-01-18 00:58:57 +00:00
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0xFF24 => self.sound.control.channel = byte.into(),
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0xFF25 => self.sound.control.select = byte.into(),
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0xFF26 => self.sound.control.status = byte.into(), // FIXME: Should we control which bytes are written to here?
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2021-01-18 01:25:53 +00:00
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0xFF40 => self.ppu.lcd_control = byte.into(),
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2021-01-18 08:22:45 +00:00
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0xFF41 => self.ppu.stat = byte.into(),
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0xFF42 => self.ppu.pos.scroll_y = byte,
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0xFF43 => self.ppu.pos.scroll_x = byte,
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0xFF44 => self.ppu.pos.line_y = byte,
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2021-01-18 01:25:53 +00:00
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0xFF47 => self.ppu.monochrome.bg_palette = byte.into(),
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2021-01-19 06:30:10 +00:00
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0xFF50 => {
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// Disable Boot ROM
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if byte != 0 {
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self.boot = None;
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}
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}
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2021-01-03 07:21:19 +00:00
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_ => unimplemented!("Unable to write to {:#06X} in I/O Registers", addr),
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};
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2020-12-24 03:24:27 +00:00
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}
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0xFF80..=0xFFFE => {
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// High RAM
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2021-01-18 03:13:59 +00:00
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self.hram.write_byte((addr - 0xFF80) as usize, byte);
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2020-12-24 03:24:27 +00:00
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}
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0xFFFF => {
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// Interupts Enable Register
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2021-01-03 07:38:31 +00:00
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self.interrupt.enable = byte.into();
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2020-12-24 03:24:27 +00:00
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}
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}
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2020-08-29 23:38:27 +00:00
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}
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2020-09-04 05:41:19 +00:00
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pub fn read_word(&self, addr: u16) -> u16 {
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2021-01-03 04:49:25 +00:00
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(self.read_byte(addr + 1) as u16) << 8 | self.read_byte(addr) as u16
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2020-08-29 23:38:27 +00:00
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}
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2020-12-23 09:43:49 +00:00
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pub fn write_word(&mut self, addr: u16, word: u16) {
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2021-01-03 04:49:25 +00:00
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self.write_byte(addr + 1, (word >> 8) as u8);
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self.write_byte(addr, (word & 0x00FF) as u8);
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2020-08-29 23:38:27 +00:00
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}
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2020-09-04 05:41:19 +00:00
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}
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