119 lines
5.2 KiB
Zig
119 lines
5.2 KiB
Zig
const std = @import("std");
|
|
const sext = @import("zba-util").sext;
|
|
const rotr = @import("zba-util").rotr;
|
|
const alignAddr = @import("zba-util").alignAddr;
|
|
|
|
const log = std.log.scoped(.half_and_signed_data_transfer);
|
|
|
|
pub fn halfAndSignedDataTransfer(comptime InstrFn: type, comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
|
|
const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
|
|
|
|
return struct {
|
|
fn inner(cpu: *Arm32, opcode: u32) void {
|
|
const rn = opcode >> 16 & 0xF;
|
|
const rd = opcode >> 12 & 0xF;
|
|
const rm = opcode & 0xF;
|
|
const imm_offset_high = opcode >> 8 & 0xF;
|
|
|
|
const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
|
|
const offset = if (I) imm_offset_high << 4 | rm else cpu.r[rm];
|
|
|
|
const modified_base = if (U) base +% offset else base -% offset;
|
|
var address = if (P) modified_base else base;
|
|
|
|
const op: u2 = @truncate(opcode >> 5);
|
|
var result: u32 = undefined;
|
|
|
|
if (L) {
|
|
switch (op) {
|
|
0b01 => {
|
|
// LDRH
|
|
result = switch (Arm32.arch) {
|
|
.v4t => rotr(u32, cpu.read(u16, address), 8 * (address & 1)),
|
|
.v5te => cpu.read(u16, alignAddr(u16, address)),
|
|
};
|
|
},
|
|
0b10 => {
|
|
// LDRSB
|
|
result = sext(u32, u8, cpu.read(u8, address));
|
|
},
|
|
0b11 => {
|
|
// LDRSH
|
|
result = switch (Arm32.arch) {
|
|
.v4t => blk: {
|
|
const value = cpu.read(u16, address);
|
|
|
|
break :blk switch (address & 1 == 1) {
|
|
true => sext(u32, u8, @as(u8, @truncate(value >> 8))),
|
|
false => sext(u32, u16, value),
|
|
};
|
|
},
|
|
.v5te => sext(u32, u16, cpu.read(u16, alignAddr(u16, address))),
|
|
};
|
|
},
|
|
0b00 => unreachable,
|
|
}
|
|
} else {
|
|
switch (op) {
|
|
0b00 => {
|
|
const B = I;
|
|
const swap_addr = cpu.r[rn];
|
|
|
|
if (B) {
|
|
// SWPB
|
|
const value = cpu.read(u8, swap_addr);
|
|
cpu.write(u8, swap_addr, @as(u8, @truncate(cpu.r[rm])));
|
|
|
|
cpu.r[rd] = value;
|
|
} else {
|
|
// SWP
|
|
const value = rotr(u32, cpu.read(u32, swap_addr), 8 * (swap_addr & 0x3));
|
|
cpu.write(u32, swap_addr, cpu.r[rm]);
|
|
|
|
cpu.r[rd] = value;
|
|
}
|
|
},
|
|
0b01 => {
|
|
// STRH
|
|
|
|
// FIXME: I shouldn't have to use @as(u16, ...) here
|
|
cpu.write(u16, address, @as(u16, @truncate(cpu.r[rd])));
|
|
},
|
|
0b10 => blk: {
|
|
// LDRD
|
|
if (Arm32.arch == .v4t) break :blk;
|
|
if (rd & 0 != 0) cpu.panic("LDRD: UNDEFINED behaviour when Rd is not even", .{});
|
|
if (rd == 0xE) cpu.panic("LDRD: UNPREDICTABLE behaviour when rd == 14", .{});
|
|
if (address & 0x7 != 0b000) cpu.panic("LDRD: UNPREDICTABLE when address (0x{X:0>8} is not double (64-bit) aligned", .{address});
|
|
|
|
// Why do we not make use of result here?
|
|
//
|
|
// It's because L is not set so there's no chance of writing an undefined
|
|
// value to the register
|
|
//
|
|
// despite this reason, this is bad design imo
|
|
// TODO: Refactor this handler
|
|
|
|
cpu.r[rd] = cpu.read(u32, address);
|
|
cpu.r[rd + 1] = cpu.read(u32, address + 4);
|
|
},
|
|
0b11 => {
|
|
// STRD
|
|
if (Arm32.arch != .v5te) cpu.panic("STRD: unsupported on arm{s}", .{@tagName(Arm32.arch)});
|
|
if (rd & 0 != 0) cpu.panic("STRD: UNDEFINED behaviour when Rd is not even", .{});
|
|
if (rd == 0xE) cpu.panic("STRD: UNPREDICTABLE behaviour when rd == 14", .{});
|
|
if (address & 0x7 != 0b000) cpu.panic("STRD: UNPREDICTABLE when address (0x{X:0>8} is not double (64-bit) aligned", .{address});
|
|
|
|
cpu.write(u32, address, cpu.r[rd]);
|
|
cpu.write(u32, address + 4, cpu.r[rd + 1]);
|
|
},
|
|
}
|
|
}
|
|
|
|
address = modified_base;
|
|
if (W and P or !P) cpu.r[rn] = address;
|
|
if (L) cpu.r[rd] = result; // // This emulates the LDR rd == rn behaviour
|
|
}
|
|
}.inner;
|
|
}
|