118 lines
5.2 KiB
Zig
118 lines
5.2 KiB
Zig
const std = @import("std");
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const sext = @import("zba-util").sext;
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const rotr = @import("zba-util").rotr;
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const log = std.log.scoped(.half_and_signed_data_transfer);
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pub fn halfAndSignedDataTransfer(comptime InstrFn: type, comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn {
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const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
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return struct {
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fn inner(cpu: *Arm32, opcode: u32) void {
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const rn = opcode >> 16 & 0xF;
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const rd = opcode >> 12 & 0xF;
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const rm = opcode & 0xF;
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const imm_offset_high = opcode >> 8 & 0xF;
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const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
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const offset = if (I) imm_offset_high << 4 | rm else cpu.r[rm];
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const modified_base = if (U) base +% offset else base -% offset;
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var address = if (P) modified_base else base;
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const op: u2 = @truncate(opcode >> 5);
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var result: u32 = undefined;
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if (L) {
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switch (op) {
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0b01 => {
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// LDRH
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result = switch (Arm32.arch) {
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.v4t => rotr(u32, cpu.read(u16, address), 8 * (address & 1)),
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.v5te => cpu.read(u16, address),
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};
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},
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0b10 => {
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// LDRSB
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result = sext(u32, u8, cpu.read(u8, address));
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},
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0b11 => {
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// LDRSH
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result = switch (Arm32.arch) {
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.v4t => blk: {
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const value = cpu.read(u16, address);
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break :blk switch (address & 1 == 1) {
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true => sext(u32, u8, @as(u8, @truncate(value >> 8))),
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false => sext(u32, u16, value),
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};
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},
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.v5te => sext(u32, u16, cpu.read(u16, address)),
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};
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},
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0b00 => unreachable,
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}
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} else {
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switch (op) {
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0b00 => {
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const B = I;
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const swap_addr = cpu.r[rn];
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if (B) {
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// SWPB
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const value = cpu.read(u8, swap_addr);
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cpu.write(u8, swap_addr, @as(u8, @truncate(cpu.r[rm])));
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cpu.r[rd] = value;
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} else {
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// SWP
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const value = rotr(u32, cpu.read(u32, swap_addr), 8 * (swap_addr & 0x3));
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cpu.write(u32, swap_addr, cpu.r[rm]);
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cpu.r[rd] = value;
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}
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},
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0b01 => {
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// STRH
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// FIXME: I shouldn't have to use @as(u16, ...) here
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cpu.write(u16, address, @as(u16, @truncate(cpu.r[rd])));
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},
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0b10 => blk: {
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// LDRD
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if (Arm32.arch == .v4t) break :blk;
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if (rd & 0 != 0) cpu.panic("LDRD: UNDEFINED behaviour when Rd is not even", .{});
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if (rd == 0xE) cpu.panic("LDRD: UNPREDICTABLE behaviour when rd == 14", .{});
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if (address & 0x7 != 0b000) cpu.panic("LDRD: UNPREDICTABLE when address (0x{X:0>8} is not double (64-bit) aligned", .{address});
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// Why do we not make use of result here?
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//
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// It's because L is not set so there's no chance of writing an undefined
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// value to the register
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//
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// despite this reason, this is bad design imo
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// TODO: Refactor this handler
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cpu.r[rd] = cpu.read(u32, address);
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cpu.r[rd + 1] = cpu.read(u32, address + 4);
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},
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0b11 => {
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// STRD
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if (Arm32.arch != .v5te) cpu.panic("STRD: unsupported on arm{s}", .{@tagName(Arm32.arch)});
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if (rd & 0 != 0) cpu.panic("STRD: UNDEFINED behaviour when Rd is not even", .{});
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if (rd == 0xE) cpu.panic("STRD: UNPREDICTABLE behaviour when rd == 14", .{});
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if (address & 0x7 != 0b000) cpu.panic("STRD: UNPREDICTABLE when address (0x{X:0>8} is not double (64-bit) aligned", .{address});
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cpu.write(u32, address, cpu.r[rd]);
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cpu.write(u32, address + 4, cpu.r[rd + 1]);
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},
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}
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}
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address = modified_base;
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if (W and P or !P) cpu.r[rn] = address;
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if (L) cpu.r[rd] = result; // // This emulates the LDR rd == rn behaviour
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}
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}.inner;
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}
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