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Author | SHA1 | Date |
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Rekai Nyangadzayi Musuka | 01746fd46f | |
Rekai Nyangadzayi Musuka | 89388dcab4 | |
Rekai Nyangadzayi Musuka | 075eb1b2fe |
25
src/arm.zig
25
src/arm.zig
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@ -84,7 +84,7 @@ pub fn Arm32(comptime arch: Architecture) type {
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};
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};
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/// Bank of Registers from other CPU Modes
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/// Bank of Registers from other CPU Modes
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const Bank = struct {
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pub const Bank = struct {
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/// Storage for r13_<mode>, r14_<mode>
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/// Storage for r13_<mode>, r14_<mode>
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/// e.g. [r13, r14, r13_svc, r14_svc]
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/// e.g. [r13, r14, r13_svc, r14_svc]
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r: [2 * 6]u32,
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r: [2 * 6]u32,
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@ -259,29 +259,6 @@ pub fn Arm32(comptime arch: Architecture) type {
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self.cpsr.mode.write(@enumToInt(next));
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self.cpsr.mode.write(@enumToInt(next));
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}
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}
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/// Advances state so that the BIOS is skipped
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///
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/// Note: This accesses the CPU's bus ptr so it only may be called
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/// once the Bus has been properly initialized
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///
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/// TODO: Make above notice impossible to do in code
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pub fn fastBoot(self: *Self) void {
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self.r = std.mem.zeroes([16]u32);
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// self.r[0] = 0x08000000;
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// self.r[1] = 0x000000EA;
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self.r[13] = 0x0300_7F00;
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self.r[15] = 0x0800_0000;
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self.bank.r[Bank.regIdx(.Irq, .R13)] = 0x0300_7FA0;
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self.bank.r[Bank.regIdx(.Supervisor, .R13)] = 0x0300_7FE0;
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// self.cpsr.raw = 0x6000001F;
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self.cpsr.raw = 0x0000_001F;
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self.bus.bios.addr_latch = 0x0000_00DC + 8;
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}
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pub fn step(self: *Self) void {
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pub fn step(self: *Self) void {
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defer {
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defer {
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if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
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if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
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