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No commits in common. "2c5d474c56043a66bbc6b1f4d83e6eeb678e6872" and "106820b444cf394f2887b44a2afbfb2c01b182ca" have entirely different histories.
2c5d474c56
...
106820b444
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@ -229,7 +229,7 @@ pub fn Arm32(comptime isa: Architecture) type {
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if (address < 0x0000_0000 + self.itcm.virt.size)
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if (address < 0x0000_0000 + self.itcm.virt.size)
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return readInt(T, self.itcm.buf[address & self.itcm.virt.mask ..][0..@sizeOf(T)]);
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return readInt(T, self.itcm.buf[address & self.itcm.virt.mask ..][0..@sizeOf(T)]);
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if (dtcm_base <= address and address < dtcm_base + dtcm_size)
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if (dtcm_base < address and address < dtcm_base + dtcm_size)
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return readInt(T, self.dtcm.buf[address & self.dtcm.virt.mask ..][0..@sizeOf(T)]);
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return readInt(T, self.dtcm.buf[address & self.dtcm.virt.mask ..][0..@sizeOf(T)]);
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}
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}
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@ -371,7 +371,7 @@ pub fn Arm32(comptime isa: Architecture) type {
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if (self.cpsr.check(Self.arch, cond)) {
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if (self.cpsr.check(Self.arch, cond)) {
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if (isa == .v5te and cond == 0b1111) {
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if (isa == .v5te and cond == 0b1111) {
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std.log.debug("TODO: Unconditional Instruction Extension Space\nopcode: 0x{X:0>8} | idx: 0x{X:} | ptr: {any}", .{ opcode, arm.idx(opcode), arm.lut[arm.idx(opcode)] });
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self.panic("TODO: Unconditional Instruction Extension Space\nopcode: 0x{X:0>8} | idx: 0x{X:} | ptr: {any}", .{ opcode, arm.idx(opcode), arm.lut[arm.idx(opcode)] });
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}
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}
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arm.lut[arm.idx(opcode)](self, opcode);
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arm.lut[arm.idx(opcode)](self, opcode);
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@ -111,13 +111,10 @@ pub fn blockDataTransfer(comptime InstrFn: type, comptime P: bool, comptime U: b
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cpu.r[i] = value;
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cpu.r[i] = value;
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if (i == 0xF) {
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if (i == 0xF) {
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const mask: u32 = if (Arm32.arch == .v5te) 1 else 3;
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cpu.r[i] &= ~@as(u32, 3); // Align r15
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cpu.r[i] &= ~mask;
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if (Arm32.arch == .v5te) cpu.cpsr.t.write(value & 1 == 1);
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if (S) cpu.setCpsr(cpu.spsr.raw); // FIXME: before or after the reload?
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cpu.pipe.reload(cpu);
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cpu.pipe.reload(cpu);
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if (S) cpu.setCpsr(cpu.spsr.raw);
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}
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}
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}
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}
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} else {
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} else {
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@ -5,24 +5,9 @@ pub fn branch(comptime InstrFn: type, comptime L: bool) InstrFn {
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return struct {
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return struct {
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fn inner(cpu: *Arm32, opcode: u32) void {
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fn inner(cpu: *Arm32, opcode: u32) void {
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const cond: u4 = @truncate(opcode >> 28);
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switch (cond) {
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0b1111 => { // BLX
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const H = L;
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const offset = sext(u32, u24, opcode) << 2 | @as(u32, @intFromBool(H)) << 1;
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cpu.r[14] = cpu.r[15] - 4;
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cpu.cpsr.t.set();
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cpu.r[15] +%= offset;
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},
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else => {
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if (L) cpu.r[14] = cpu.r[15] - 4;
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if (L) cpu.r[14] = cpu.r[15] - 4;
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cpu.r[15] +%= sext(u32, u24, opcode) << 2;
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cpu.r[15] +%= sext(u32, u24, opcode) << 2;
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},
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}
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cpu.pipe.reload(cpu);
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cpu.pipe.reload(cpu);
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}
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}
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}.inner;
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}.inner;
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@ -108,21 +108,26 @@ pub fn control(comptime InstrFn: type, comptime I: bool, comptime op: u6) InstrF
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const rm = opcode & 0xF;
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const rm = opcode & 0xF;
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const rs = opcode >> 8 & 0xF;
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const rs = opcode >> 8 & 0xF;
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const rdlo = opcode >> 12 & 0xF;
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const rd_lo = opcode >> 12 & 0xF;
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const rdhi = opcode >> 16 & 0xF;
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const rd_hi = opcode >> 16 & 0xF;
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const left: i64 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rm] >> 16 * X))));
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const left: i32 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rm] >> 16 * X))));
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const right: i64 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rs] >> 16 * Y))));
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const right: i32 = @as(i16, @bitCast(@as(u16, @truncate(cpu.r[rs] >> 16 * Y))));
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// TODO: de-clutter this lmao
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const rdlo_val: i32 = @bitCast(cpu.r[rd_lo]);
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const product = left * right;
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const product = left * right;
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const rdhi_val: i32 = @bitCast(cpu.r[rdhi]);
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// WHY DOESN'T THIS WORK????????
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const rdlo_val: i32 = @bitCast(cpu.r[rdlo]);
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const accumulate = @as(i64, rdhi_val) << 32 | rdlo_val;
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cpu.r[rd_lo] = @bitCast(rdlo_val + product);
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const sum = product +% accumulate;
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cpu.r[rd_hi] = blk: {
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// FIXME: I think this has to do with correcting sign values?
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const offset_thing: i32 = @bitCast(if (product < 0) 0xFFFF_FFFF else @as(u32, 0));
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cpu.r[rdhi] = @bitCast(@as(i32, @truncate(sum >> 32)));
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const rdhi_val: i32 = @bitCast(cpu.r[rd_hi]);
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cpu.r[rdlo] = @bitCast(@as(i32, @truncate(sum)));
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break :blk @bitCast(rdhi_val + offset_thing + @addWithOverflow(rdlo_val, product)[1]);
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};
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},
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},
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0b01_1000, 0b01_1100 => { // SMLAW<y>
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0b01_1000, 0b01_1100 => { // SMLAW<y>
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const Y = op >> 2 & 1;
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const Y = op >> 2 & 1;
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@ -173,6 +178,16 @@ pub fn control(comptime InstrFn: type, comptime I: bool, comptime op: u6) InstrF
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}
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}
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}
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}
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// TODO: make generic on any integer?
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inline fn carryFrom(left: i32, right: i32) u1 {
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const _left: u32 = @bitCast(left);
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const _right: u32 = @bitCast(right);
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const sum = @as(u64, _left) + @as(u64, _right);
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return @intCast(sum >> 32 & 1);
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}
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inline fn msr(comptime R: bool, comptime imm: bool, cpu: *Arm32, opcode: u32) void {
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inline fn msr(comptime R: bool, comptime imm: bool, cpu: *Arm32, opcode: u32) void {
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const field_mask: u4 = @truncate(opcode >> 16 & 0xF);
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const field_mask: u4 = @truncate(opcode >> 16 & 0xF);
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const rm_idx = opcode & 0xF;
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const rm_idx = opcode & 0xF;
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@ -49,15 +49,7 @@ pub fn singleDataTransfer(comptime InstrFn: type, comptime I: bool, comptime P:
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if (L) {
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if (L) {
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// This emulates the LDR rd == rn behaviour
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// This emulates the LDR rd == rn behaviour
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cpu.r[rd] = result;
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cpu.r[rd] = result;
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if (rd == 0xF) cpu.pipe.reload(cpu);
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if (rd == 0xF) {
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if (Arm32.arch == .v5te) {
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cpu.r[rd] &= ~@as(u32, 1);
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cpu.cpsr.t.write(result & 1 == 1);
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}
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cpu.pipe.reload(cpu);
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}
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}
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}
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}
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}
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}.inner;
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}.inner;
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@ -32,8 +32,6 @@ pub fn fmt14(comptime InstrFn: type, comptime L: bool, comptime R: bool) InstrFn
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if (L) {
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if (L) {
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const value = cpu.read(u32, address);
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const value = cpu.read(u32, address);
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cpu.r[15] = value & ~@as(u32, 1);
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cpu.r[15] = value & ~@as(u32, 1);
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if (Arm32.arch == .v5te) cpu.cpsr.t.write(value & 1 == 1);
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cpu.pipe.reload(cpu);
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cpu.pipe.reload(cpu);
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} else {
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} else {
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cpu.write(u32, address, cpu.r[14]);
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cpu.write(u32, address, cpu.r[14]);
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@ -17,37 +17,38 @@ pub fn fmt16(comptime InstrFn: type, comptime cond: u4) InstrFn {
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}.inner;
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}.inner;
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}
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}
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pub fn linkExchange(comptime InstrFn: type, comptime H: u2) InstrFn {
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pub fn fmt18(comptime InstrFn: type) InstrFn {
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const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
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return struct {
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// B but conditional
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fn inner(cpu: *Arm32, opcode: u16) void {
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cpu.r[15] +%= sext(u32, u11, opcode & 0x7FF) << 1;
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cpu.pipe.reload(cpu);
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}
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}.inner;
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}
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pub fn fmt19(comptime InstrFn: type, comptime is_low: bool) InstrFn {
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const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
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const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
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return struct {
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return struct {
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fn inner(cpu: *Arm32, opcode: u16) void {
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fn inner(cpu: *Arm32, opcode: u16) void {
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// BL
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const offset = opcode & 0x7FF;
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const offset = opcode & 0x7FF;
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switch (H) {
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if (is_low) {
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0b00 => { // Unconditional Branch
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// Instruction 2
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cpu.r[15] +%= sext(u32, u11, opcode & 0x7FF) << 1;
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const next_opcode = cpu.r[15] - 2;
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cpu.pipe.reload(cpu);
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},
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0b01 => { // BLX Pt. 2
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if (Arm32.arch == .v4t) cpu.panic("attempted to execute THUMB BLX(1), despite ARMv4T CPU", .{});
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const next_addr = cpu.r[15] - 2;
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cpu.r[15] = (cpu.r[14] +% (offset << 1)) & ~@as(u32, 0x3);
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cpu.r[14] = next_addr | 1;
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cpu.cpsr.t.unset();
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cpu.pipe.reload(cpu);
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},
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0b10 => cpu.r[14] = cpu.r[15] +% (sext(u32, u11, offset) << 12), // BL / BLX Pt. 1
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0b11 => { // BL Pt. 2
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const next_addr = cpu.r[15] - 2;
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cpu.r[15] = cpu.r[14] +% (offset << 1);
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cpu.r[15] = cpu.r[14] +% (offset << 1);
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cpu.r[14] = next_addr | 1;
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cpu.r[14] = next_opcode | 1;
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cpu.pipe.reload(cpu);
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cpu.pipe.reload(cpu);
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},
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} else {
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// Instruction 1
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const lr_offset = sext(u32, u11, offset) << 12;
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cpu.r[14] = (cpu.r[15] +% lr_offset) & ~@as(u32, 1);
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}
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}
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}
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}
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}.inner;
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}.inner;
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@ -60,17 +60,6 @@ pub fn fmt5(comptime InstrFn: type, comptime op: u2, comptime h1: u1, comptime h
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const rs = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
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const rs = @as(u4, h2) << 3 | (opcode >> 3 & 0x7);
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const rd = @as(u4, h1) << 3 | (opcode & 0x7);
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const rd = @as(u4, h1) << 3 | (opcode & 0x7);
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if (Arm32.arch == .v5te and op == 0b11 and h1 == 0b1) {
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// BLX
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const rm = rs;
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cpu.r[14] = (cpu.r[15] - 2) | 1;
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cpu.cpsr.t.write(cpu.r[rm] & 1 == 1);
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cpu.r[15] = cpu.r[rm] & ~@as(u32, 1);
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cpu.pipe.reload(cpu);
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}
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const op1 = cpu.r[rd];
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const op1 = cpu.r[rd];
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const op2 = cpu.r[rs];
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const op2 = cpu.r[rs];
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@ -216,13 +205,3 @@ pub fn fmt13(comptime InstrFn: type, comptime S: bool) InstrFn {
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}
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}
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}.inner;
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}.inner;
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}
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}
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pub fn bkpt(comptime InstrFn: type) InstrFn {
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const Arm32 = @typeInfo(@typeInfo(@typeInfo(InstrFn).Pointer.child).Fn.params[0].type.?).Pointer.child;
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return struct {
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fn inner(cpu: *Arm32, _: u16) void {
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cpu.panic("TODO: handle THUMB BKPT", .{});
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}
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}.inner;
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}
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@ -205,9 +205,12 @@ pub const thumb = struct {
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const cond = i >> 2 & 0xF;
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const cond = i >> 2 & 0xF;
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break :blk branch.fmt16(InstrFn, cond);
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break :blk branch.fmt16(InstrFn, cond);
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},
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},
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0b110, 0b111 => blk: {
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0b110 => branch.fmt18(
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const H = i >> 5 & 0x3;
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InstrFn,
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break :blk branch.linkExchange(InstrFn, H);
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),
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0b111 => blk: {
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const is_low = i >> 5 & 1 == 1;
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break :blk branch.fmt19(InstrFn, is_low);
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},
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},
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},
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},
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};
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};
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@ -149,8 +149,6 @@ pub const thumb = struct {
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return comptime comptime_blk: {
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return comptime comptime_blk: {
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@setEvalBranchQuota(5025); // This is exact
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@setEvalBranchQuota(5025); // This is exact
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var table = [_]InstrFn{und} ** 0x400;
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var table = [_]InstrFn{und} ** 0x400;
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// 9 8 7 6 5 4 3 2 1 0
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// 15 14 13 12 11 10 9 8 7 6
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for (&table, 0..) |*handler, i| {
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for (&table, 0..) |*handler, i| {
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handler.* = switch (@as(u3, i >> 7 & 0x7)) {
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handler.* = switch (@as(u3, i >> 7 & 0x7)) {
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@ -212,19 +210,14 @@ pub const thumb = struct {
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const rd = i >> 2 & 0x7;
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const rd = i >> 2 & 0x7;
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break :blk processing.fmt12(InstrFn, isSP, rd);
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break :blk processing.fmt12(InstrFn, isSP, rd);
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},
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},
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0b011 => switch (@as(u2, @truncate(i >> 3 & 0x3))) {
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0b011 => if (i >> 4 & 1 == 1) blk: {
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0b10 => blk: {
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// PUSH / POP
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const L = i >> 5 & 1 == 1;
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const L = i >> 5 & 1 == 1;
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const R = i >> 2 & 1 == 1;
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const R = i >> 2 & 1 == 1;
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break :blk block_transfer.fmt14(InstrFn, L, R);
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break :blk block_transfer.fmt14(InstrFn, L, R);
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},
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} else blk: {
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0b11 => processing.bkpt(InstrFn),
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else => blk: {
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const S = i >> 1 & 1 == 1;
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const S = i >> 1 & 1 == 1;
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break :blk processing.fmt13(InstrFn, S);
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break :blk processing.fmt13(InstrFn, S);
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},
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},
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},
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0b100 => blk: {
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0b100 => blk: {
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const L = i >> 5 & 1 == 1;
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const L = i >> 5 & 1 == 1;
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const rb = i >> 2 & 0x7;
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const rb = i >> 2 & 0x7;
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@ -237,9 +230,12 @@ pub const thumb = struct {
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const cond = i >> 2 & 0xF;
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const cond = i >> 2 & 0xF;
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break :blk branch.fmt16(InstrFn, cond);
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break :blk branch.fmt16(InstrFn, cond);
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},
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},
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0b110, 0b111 => blk: {
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0b110 => branch.fmt18(
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const H = i >> 5 & 0x3;
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InstrFn,
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break :blk branch.linkExchange(InstrFn, H);
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),
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0b111 => blk: {
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const is_low = i >> 5 & 1 == 1;
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break :blk branch.fmt19(InstrFn, is_low);
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},
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},
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},
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},
|
||||||
};
|
};
|
||||||
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