chore: drop *Bus argument from the InstrFn LUT

src/arm.zig

@@ -50,6 +50,7 @@ pub fn Arm32(comptime arch: Architecture) type {
             .v5te => @import("arm/v5te.zig").thumb,
         };
 
+        // FIXME: What about .v5te?
         const Pipeline = struct {
             stage: [2]?u32,
             flushed: bool,
@@ -147,7 +148,7 @@ pub fn Arm32(comptime arch: Architecture) type {
         };
 
         pub fn init(scheduler: Scheduler, bus: Bus) Self {
-            return Self{
+            return .{
                 .sched = scheduler,
                 .bus = bus,
                 .cpsr = .{ .raw = 0x0000_001F },
@@ -155,6 +156,16 @@ pub fn Arm32(comptime arch: Architecture) type {
             };
         }
 
+        // CPU needs it's own read/write fns due to ICTM and DCTM present in v5te
+        // I considered implementing Bus.cpu_read and Bus.cpu_write but ended up considering that a bit too leaky
+        pub fn read(self: *Self, comptime T: type, address: u32) T {
+            return self.bus.read(T, address);
+        }
+
+        pub fn write(self: *Self, comptime T: type, address: u32, value: T) void {
+            return self.bus.write(T, address, value);
+        }
+
         // FIXME: Resetting disables logging (if enabled)
         pub fn reset(self: *Self) void {
             self.* = .{
@@ -276,12 +287,12 @@ pub fn Arm32(comptime arch: Architecture) type {
 
             if (self.cpsr.t.read()) {
                 const opcode: u16 = @truncate(self.pipe.step(self, u16) orelse return);
-                thumb.lut[thumb.idx(opcode)](self, self.bus, opcode);
+                thumb.lut[thumb.idx(opcode)](self, opcode);
             } else {
                 const opcode = self.pipe.step(self, u32) orelse return;
 
                 if (self.cpsr.check(@truncate(opcode >> 28))) {
-                    arm.lut[arm.idx(opcode)](self, self.bus, opcode);
+                    arm.lut[arm.idx(opcode)](self, opcode);
                 }
             }
         }
@@ -298,7 +309,7 @@ pub fn Arm32(comptime arch: Architecture) type {
             // const tick_cache = self.sched.tick;
             // defer self.sched.tick = tick_cache + Bus.fetch_timings[@boolToInt(T == u32)][@truncate(u4, address >> 24)];
 
-            return self.bus.read(T, address);
+            return self.read(T, address);
         }
 
         pub fn panic(self: *const Self, comptime format: []const u8, args: anytype) noreturn {