feat(v5te): let cp15 affect more tcm behaviours

cp15 can now enable/disable ITCM/DTCM. cp15 can also now enable/disable load mode.
TODO: load mode doesn't effect SWP/SWPB for some reason?

src/arm/cpu/arm/coprocessor.zig

@@ -1,4 +1,5 @@
 const std = @import("std");
+const Bit = @import("bitfield").Bit;
 
 const log = std.log.scoped(.coprocessor_handler);
 
@@ -118,6 +119,13 @@ pub fn registerTransfer(comptime InstrFn: type, comptime opcode1: u3, comptime L
                     // TODO: there has to be a better way.....
 
                     // ICTM / DTCM Stuff
+                    const ctrl: cp15.Control = @bitCast(cpu.cp15.read(0, 1, 0, 0));
+                    cpu.dtcm.enabled = ctrl.dtcm_enable.read();
+                    cpu.dtcm.load_mode = ctrl.dtcm_load_mode.read();
+
+                    cpu.itcm.enabled = ctrl.itcm_enable.read();
+                    cpu.itcm.load_mode = ctrl.itcm_load_mode.read();
+
                     const dtcm_size_base = cpu.cp15.read(0, 9, 1, 0); // mrc 0, c9, c1, 0
                     const itcm_size_base = cpu.cp15.read(0, 9, 1, 1); // mrc 0, c9, c1, 1
 
@@ -146,3 +154,22 @@ pub fn dataProcessing(comptime InstrFn: type, comptime opcode1: u4, comptime opc
         }
     }.inner;
 }
+
+const cp15 = struct {
+    // Only the bits that are R/W on the NDS (for now)
+    const Control = extern union {
+        pu_enable: Bit(u32, 0),
+        unified_cache: Bit(u32, 2),
+        endian: Bit(u32, 7),
+        instruction_cache: Bit(u32, 12),
+        exception_vectors: Bit(u32, 13),
+        cache_replacement: Bit(u32, 14),
+        pre_armv5_mode: Bit(u32, 15),
+        dtcm_enable: Bit(u32, 16),
+        dtcm_load_mode: Bit(u32, 17),
+        itcm_enable: Bit(u32, 18),
+        itcm_load_mode: Bit(u32, 19),
+
+        raw: u32,
+    };
+};