fix: remove redundant casts from zig fmt
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@@ -58,6 +58,7 @@ pub fn Arm32(comptime arch: Architecture) type {
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return self.stage[0] != null and self.stage[1] != null;
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}
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// TODO: Why does this not return T?
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pub fn step(self: *@This(), cpu: *Self, comptime T: type) ?u32 {
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comptime std.debug.assert(T == u32 or T == u16);
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@@ -174,7 +175,7 @@ pub fn Arm32(comptime arch: Architecture) type {
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}
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pub fn setCpsr(self: *Self, value: u32) void {
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if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@as(u5, @truncate(value & 0x1F)));
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if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(value & 0x1F));
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self.cpsr.raw = value;
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}
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@@ -267,12 +268,12 @@ pub fn Arm32(comptime arch: Architecture) type {
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}
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if (self.cpsr.t.read()) {
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const opcode = @as(u16, @truncate(self.pipe.step(self, u16) orelse return));
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const opcode: u16 = @truncate(self.pipe.step(self, u16) orelse return);
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thumb.lut[thumb.idx(opcode)](self, self.bus, opcode);
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} else {
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const opcode = self.pipe.step(self, u32) orelse return;
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if (self.cpsr.check(@as(u4, @truncate(opcode >> 28)))) {
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if (self.cpsr.check(@truncate(opcode >> 28))) {
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arm.lut[arm.idx(opcode)](self, self.bus, opcode);
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}
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}
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@@ -391,7 +392,7 @@ pub const PSR = extern union {
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}
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pub inline fn check(self: @This(), cond: u4) bool {
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const flags = @as(u4, @truncate(self.raw >> 28));
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const flags: u4 = @truncate(self.raw >> 28);
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return condition_lut[cond] & (@as(u16, 1) << flags) != 0;
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}
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