paoda/arm32
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix: remove redundant casts from zig fmt

Browse Source
This commit is contained in:
Rekai Nyangadzayi Musuka
2023-07-11 00:39:14 -05:00
parent a831ab22fe
commit 6c81608c59
13 changed files with 56 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/arm/cpu/thumb/alu.zig
View File

@@ -26,12 +26,12 @@ pub fn fmt4(comptime InstrFn: type, comptime op: u4) InstrFn {
switch (op) {
0x0 => result = op1 & op2, // AND
0x1 => result = op1 ^ op2, // EOR
0x2 => result = lsl(true, &cpu.cpsr, op1, @as(u8, @truncate(op2))), // LSL
0x3 => result = lsr(true, &cpu.cpsr, op1, @as(u8, @truncate(op2))), // LSR
0x4 => result = asr(true, &cpu.cpsr, op1, @as(u8, @truncate(op2))), // ASR
0x2 => result = lsl(true, &cpu.cpsr, op1, @truncate(op2)), // LSL
0x3 => result = lsr(true, &cpu.cpsr, op1, @truncate(op2)), // LSR
0x4 => result = asr(true, &cpu.cpsr, op1, @truncate(op2)), // ASR
0x5 => result = adc(&overflow, op1, op2, carry), // ADC
0x6 => result = sbc(op1, op2, carry), // SBC
0x7 => result = ror(true, &cpu.cpsr, op1, @as(u8, @truncate(op2))), // ROR
0x7 => result = ror(true, &cpu.cpsr, op1, @truncate(op2)), // ROR
0x8 => result = op1 & op2, // TST
0x9 => result = 0 -% op2, // NEG
0xA => result = op1 -% op2, // CMP
@@ -42,7 +42,7 @@ pub fn fmt4(comptime InstrFn: type, comptime op: u4) InstrFn {
overflow = tmp[1];
},
0xC => result = op1 | op2, // ORR
0xD => result = @as(u32, @truncate(@as(u64, op2) * @as(u64, op1))),
0xD => result = @truncate(@as(u64, op2) * @as(u64, op1)),
0xE => result = op1 & ~op2,
0xF => result = ~op2,
}

6
src/arm/cpu/thumb/data_processing.zig
View File

@@ -14,7 +14,7 @@ pub fn fmt1(comptime InstrFn: type, comptime op: u2, comptime offset: u5) InstrF
const rs = opcode >> 3 & 0x7;
const rd = opcode & 0x7;
const result = switch (op) {
const result: u32 = switch (op) {
0b00 => blk: {
// LSL
if (offset == 0) {
@@ -36,7 +36,7 @@ pub fn fmt1(comptime InstrFn: type, comptime op: u2, comptime offset: u5) InstrF
// ASR
if (offset == 0) {
cpu.cpsr.c.write(cpu.r[rs] >> 31 & 1 == 1);
break :blk @as(u32, @bitCast(@as(i32, @bitCast(cpu.r[rs])) >> 31));
break :blk @bitCast(@as(i32, @bitCast(cpu.r[rs])) >> 31);
} else {
break :blk asr(true, &cpu.cpsr, cpu.r[rs], offset);
}
@@ -115,7 +115,7 @@ pub fn fmt2(comptime InstrFn: type, comptime I: bool, is_sub: bool, rn: u3) Inst
return struct {
fn inner(cpu: Arm32, _: Bus, opcode: u16) void {
const rs = opcode >> 3 & 0x7;
const rd = @as(u3, @truncate(opcode));
const rd: u3 = @truncate(opcode);
const op1 = cpu.r[rs];
const op2: u32 = if (I) rn else cpu.r[rn];

10
src/arm/cpu/thumb/data_transfer.zig
View File

@@ -33,6 +33,8 @@ pub fn fmt78(comptime InstrFn: type, comptime op: u2, comptime T: bool) InstrFn
switch (op) {
0b00 => {
// STRH
// FIXME: I shouldn't have to use @as(u8, ...) here
bus.write(u16, address, @as(u16, @truncate(cpu.r[rd])));
},
0b01 => {
@@ -47,6 +49,8 @@ pub fn fmt78(comptime InstrFn: type, comptime op: u2, comptime T: bool) InstrFn
0b11 => {
// LDRSH
const value = bus.read(u16, address);
// FIXME: I shouldn't have to use @as(u8, ...) here
cpu.r[rd] = if (address & 1 == 1) sext(u32, u8, @as(u8, @truncate(value >> 8))) else sext(u32, u16, value);
},
}
@@ -59,6 +63,8 @@ pub fn fmt78(comptime InstrFn: type, comptime op: u2, comptime T: bool) InstrFn
},
0b01 => {
// STRB
// FIXME: I shouldn't have to use @as(u8, ...) here
bus.write(u8, address, @as(u8, @truncate(cpu.r[rd])));
},
0b10 => {
@@ -99,6 +105,8 @@ pub fn fmt9(comptime InstrFn: type, comptime B: bool, comptime L: bool, comptime
if (B) {
// STRB
const address = cpu.r[rb] + offset;
// FIXME: I shouldn't have to use @as(u8, ...) here
bus.write(u8, address, @as(u8, @truncate(cpu.r[rd])));
} else {
// STR
@@ -126,6 +134,8 @@ pub fn fmt10(comptime InstrFn: type, comptime L: bool, comptime offset: u5) Inst
cpu.r[rd] = rotr(u32, value, 8 * (address & 1));
} else {
// STRH
// FIXME: I shouldn't have to use @as(u8, ...) here
bus.write(u16, address, @as(u16, @truncate(cpu.r[rd])));
}
}