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fix(v5te): set T on select load instrs when rd == 15

This commit is contained in:
Rekai Nyangadzayi Musuka 2023-09-20 00:03:59 -05:00
parent 502647806c
commit 4d3814db36
3 changed files with 17 additions and 4 deletions
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9
src/arm/cpu/arm/block_data_transfer.zig
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@ -111,10 +111,13 @@ pub fn blockDataTransfer(comptime InstrFn: type, comptime P: bool, comptime U: b
cpu.r[i] = value; cpu.r[i] = value;
if (i == 0xF) { if (i == 0xF) {
cpu.r[i] &= ~@as(u32, 3); // Align r15 const mask: u32 = if (Arm32.arch == .v5te) 1 else 3;
cpu.pipe.reload(cpu); cpu.r[i] &= ~mask;
if (S) cpu.setCpsr(cpu.spsr.raw); if (Arm32.arch == .v5te) cpu.cpsr.t.write(value & 1 == 1);
if (S) cpu.setCpsr(cpu.spsr.raw); // FIXME: before or after the reload?
cpu.pipe.reload(cpu);
} }
} }
} else { } else {

10
src/arm/cpu/arm/single_data_transfer.zig
View File

@ -49,7 +49,15 @@ pub fn singleDataTransfer(comptime InstrFn: type, comptime I: bool, comptime P:
if (L) { if (L) {
// This emulates the LDR rd == rn behaviour // This emulates the LDR rd == rn behaviour
cpu.r[rd] = result; cpu.r[rd] = result;
if (rd == 0xF) cpu.pipe.reload(cpu);
if (rd == 0xF) {
if (Arm32.arch == .v5te) {
cpu.r[rd] &= ~@as(u32, 1);
cpu.cpsr.t.write(result & 1 == 1);
}
cpu.pipe.reload(cpu);
}
} }
} }
}.inner; }.inner;

2
src/arm/cpu/thumb/block_data_transfer.zig
View File

@ -32,6 +32,8 @@ pub fn fmt14(comptime InstrFn: type, comptime L: bool, comptime R: bool) InstrFn
if (L) { if (L) {
const value = cpu.read(u32, address); const value = cpu.read(u32, address);
cpu.r[15] = value & ~@as(u32, 1); cpu.r[15] = value & ~@as(u32, 1);
if (Arm32.arch == .v5te) cpu.cpsr.t.write(value & 1 == 1);
cpu.pipe.reload(cpu); cpu.pipe.reload(cpu);
} else { } else {
cpu.write(u32, address, cpu.r[14]); cpu.write(u32, address, cpu.r[14]);