fix(v5te): set T on select load instrs when rd == 15

2023-09-20 00:03:59 -05:00
parent 502647806c
commit 4d3814db36
3 changed files with 17 additions and 4 deletions
--- a/src/arm/cpu/thumb/block_data_transfer.zig
+++ b/src/arm/cpu/thumb/block_data_transfer.zig
@@ -32,6 +32,8 @@ pub fn fmt14(comptime InstrFn: type, comptime L: bool, comptime R: bool) InstrFn
                if (L) {
                    const value = cpu.read(u32, address);
                    cpu.r[15] = value & ~@as(u32, 1);
+
+                    if (Arm32.arch == .v5te) cpu.cpsr.t.write(value & 1 == 1);
                    cpu.pipe.reload(cpu);
                } else {
                    cpu.write(u32, address, cpu.r[14]);