399 lines
14 KiB
Zig
399 lines
14 KiB
Zig
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const std = @import("std");
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const Architecture = enum { v4t, v5te };
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const Interpreter = @import("lib.zig").Interpreter;
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const Bus = @import("lib.zig").Bus;
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const Scheduler = @import("lib.zig").Scheduler;
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const Bitfield = @import("bitfield").Bitfield;
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const Bit = @import("bitfield").Bit;
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const condition_lut = [_]u16{
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0xF0F0, // EQ - Equal
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0x0F0F, // NE - Not Equal
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0xCCCC, // CS - Unsigned higher or same
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0x3333, // CC - Unsigned lower
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0xFF00, // MI - Negative
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0x00FF, // PL - Positive or Zero
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0xAAAA, // VS - Overflow
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0x5555, // VC - No Overflow
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0x0C0C, // HI - unsigned hierh
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0xF3F3, // LS - unsigned lower or same
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0xAA55, // GE - greater or equal
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0x55AA, // LT - less than
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0x0A05, // GT - greater than
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0xF5FA, // LE - less than or equal
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0xFFFF, // AL - always
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0x0000, // NV - never
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};
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pub fn Arm32(comptime arch: Architecture) type {
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return struct {
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const Self = @This();
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r: [16]u32 = [_]u32{0x00} ** 16,
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pipe: Pipeline = Pipeline.init(),
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sched: Scheduler,
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bus: Bus,
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cpsr: PSR,
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spsr: PSR,
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bank: Bank = Bank.create(),
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const arm = @import("arm/v4t.zig").arm(Self);
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const thumb = @import("arm/v4t.zig").thumb(Self);
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const Pipeline = struct {
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stage: [2]?u32,
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flushed: bool,
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fn init() @This() {
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return .{
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.stage = [_]?u32{null} ** 2,
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.flushed = false,
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};
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}
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pub fn isFull(self: *const @This()) bool {
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return self.stage[0] != null and self.stage[1] != null;
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}
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pub fn step(self: *@This(), cpu: *Self, comptime T: type) ?u32 {
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comptime std.debug.assert(T == u32 or T == u16);
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const opcode = self.stage[0];
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self.stage[0] = self.stage[1];
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self.stage[1] = cpu.fetch(T, cpu.r[15]);
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return opcode;
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}
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pub fn reload(self: *@This(), cpu: *Self) void {
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if (cpu.cpsr.t.read()) {
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self.stage[0] = cpu.fetch(u16, cpu.r[15]);
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self.stage[1] = cpu.fetch(u16, cpu.r[15] + 2);
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cpu.r[15] += 4;
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} else {
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self.stage[0] = cpu.fetch(u32, cpu.r[15]);
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self.stage[1] = cpu.fetch(u32, cpu.r[15] + 4);
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cpu.r[15] += 8;
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}
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self.flushed = true;
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}
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};
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/// Bank of Registers from other CPU Modes
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pub const Bank = struct {
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/// Storage for r13_<mode>, r14_<mode>
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/// e.g. [r13, r14, r13_svc, r14_svc]
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r: [2 * 6]u32,
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/// Storage for R8_fiq -> R12_fiq and their normal counterparts
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/// e.g [r[0 + 8], fiq_r[0 + 8], r[1 + 8], fiq_r[1 + 8]...]
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fiq: [2 * 5]u32,
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spsr: [5]PSR,
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const Kind = enum(u1) {
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R13 = 0,
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R14,
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};
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pub fn create() Bank {
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return .{
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.r = [_]u32{0x00} ** 12,
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.fiq = [_]u32{0x00} ** 10,
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.spsr = [_]PSR{.{ .raw = 0x0000_0000 }} ** 5,
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};
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}
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// public so that we can set up fast-boot
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pub inline fn regIdx(mode: Mode, kind: Kind) usize {
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const idx: usize = switch (mode) {
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.User, .System => 0,
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.Supervisor => 1,
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.Abort => 2,
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.Undefined => 3,
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.Irq => 4,
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.Fiq => 5,
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};
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return (idx * 2) + if (kind == .R14) @as(usize, 1) else 0;
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}
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inline fn spsrIdx(mode: Mode) usize {
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return switch (mode) {
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.Supervisor => 0,
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.Abort => 1,
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.Undefined => 2,
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.Irq => 3,
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.Fiq => 4,
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else => std.debug.panic("[CPU/Mode] {} does not have a SPSR Register", .{mode}),
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};
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}
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inline fn fiqIdx(i: usize, mode: Mode) usize {
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return (i * 2) + if (mode == .Fiq) @as(usize, 1) else 0;
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}
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};
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pub fn init(scheduler: Scheduler, bus: Bus) Self {
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return Self{
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.sched = scheduler,
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.bus = bus,
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.cpsr = .{ .raw = 0x0000_001F },
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.spsr = .{ .raw = 0x0000_0000 },
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};
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}
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// FIXME: Resetting disables logging (if enabled)
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pub fn reset(self: *Self) void {
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self.* = .{
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.sched = self.sched,
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.bus = self.bus,
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.cpsr = .{ .raw = 0x0000_001F },
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.spsr = .{ .raw = 0x0000_0000 },
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};
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}
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pub inline fn hasSPSR(self: *const Self) bool {
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const mode = Mode.getChecked(self, self.cpsr.mode.read());
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return switch (mode) {
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.System, .User => false,
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else => true,
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};
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}
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pub inline fn isPrivileged(self: *const Self) bool {
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const mode = Mode.getChecked(self, self.cpsr.mode.read());
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return switch (mode) {
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.User => false,
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else => true,
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};
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}
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pub fn setCpsr(self: *Self, value: u32) void {
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if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
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self.cpsr.raw = value;
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}
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fn changeModeFromIdx(self: *Self, next: u5) void {
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self.changeMode(Mode.getChecked(self, next));
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}
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pub fn setUserModeRegister(self: *Self, idx: usize, value: u32) void {
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const current = Mode.getChecked(self, self.cpsr.mode.read());
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switch (idx) {
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8...12 => {
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if (current == .Fiq) {
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self.bank.fiq[Bank.fiqIdx(idx - 8, .User)] = value;
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} else self.r[idx] = value;
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},
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13, 14 => switch (current) {
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.User, .System => self.r[idx] = value,
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else => {
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const kind = std.meta.intToEnum(Bank.Kind, idx - 13) catch unreachable;
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self.bank.r[Bank.regIdx(.User, kind)] = value;
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},
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},
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else => self.r[idx] = value, // R0 -> R7 and R15
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}
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}
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pub fn getUserModeRegister(self: *Self, idx: usize) u32 {
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const current = Mode.getChecked(self, self.cpsr.mode.read());
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return switch (idx) {
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8...12 => if (current == .Fiq) self.bank.fiq[Bank.fiqIdx(idx - 8, .User)] else self.r[idx],
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13, 14 => switch (current) {
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.User, .System => self.r[idx],
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else => blk: {
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const kind = std.meta.intToEnum(Bank.Kind, idx - 13) catch unreachable;
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break :blk self.bank.r[Bank.regIdx(.User, kind)];
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},
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},
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else => self.r[idx], // R0 -> R7 and R15
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};
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}
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pub fn changeMode(self: *Self, next: Mode) void {
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const now = Mode.getChecked(self, self.cpsr.mode.read());
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// Bank R8 -> r12
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for (0..5) |i| {
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self.bank.fiq[Bank.fiqIdx(i, now)] = self.r[8 + i];
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}
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// Bank r13, r14, SPSR
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switch (now) {
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.User, .System => {
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self.bank.r[Bank.regIdx(now, .R13)] = self.r[13];
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self.bank.r[Bank.regIdx(now, .R14)] = self.r[14];
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},
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else => {
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self.bank.r[Bank.regIdx(now, .R13)] = self.r[13];
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self.bank.r[Bank.regIdx(now, .R14)] = self.r[14];
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self.bank.spsr[Bank.spsrIdx(now)] = self.spsr;
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},
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}
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// Grab R8 -> R12
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for (0..5) |i| {
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self.r[8 + i] = self.bank.fiq[Bank.fiqIdx(i, next)];
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}
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// Grab r13, r14, SPSR
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switch (next) {
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.User, .System => {
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self.r[13] = self.bank.r[Bank.regIdx(next, .R13)];
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self.r[14] = self.bank.r[Bank.regIdx(next, .R14)];
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},
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else => {
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self.r[13] = self.bank.r[Bank.regIdx(next, .R13)];
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self.r[14] = self.bank.r[Bank.regIdx(next, .R14)];
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self.spsr = self.bank.spsr[Bank.spsrIdx(next)];
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},
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}
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self.cpsr.mode.write(@enumToInt(next));
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}
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pub fn step(self: *Self) void {
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defer {
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if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
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self.pipe.flushed = false;
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}
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if (self.cpsr.t.read()) {
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const opcode = @truncate(u16, self.pipe.step(self, u16) orelse return);
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thumb.lut[thumb.idx(opcode)](self, self.bus, opcode);
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} else {
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const opcode = self.pipe.step(self, u32) orelse return;
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if (self.cpsr.check(@truncate(u4, opcode >> 28))) {
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arm.lut[arm.idx(opcode)](self, self.bus, opcode);
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}
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}
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}
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inline fn fetch(self: *Self, comptime T: type, address: u32) T {
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comptime std.debug.assert(T == u32 or T == u16); // Opcode may be 32-bit (ARM) or 16-bit (THUMB)
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// Bus.read will advance the scheduler. There are different timings for CPU fetches,
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// so we want to undo what Bus.read will apply. We can do this by caching the current tick
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// This is very dumb.
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//
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// FIXME: Please rework this
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// FIXME: Please Re-enable this
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// const tick_cache = self.sched.tick;
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// defer self.sched.tick = tick_cache + Bus.fetch_timings[@boolToInt(T == u32)][@truncate(u4, address >> 24)];
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return self.bus.read(T, address);
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}
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pub fn panic(self: *const Self, comptime format: []const u8, args: anytype) noreturn {
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var i: usize = 0;
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while (i < 16) : (i += 4) {
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const i_1 = i + 1;
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const i_2 = i + 2;
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const i_3 = i + 3;
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std.debug.print("R{}: 0x{X:0>8}\tR{}: 0x{X:0>8}\tR{}: 0x{X:0>8}\tR{}: 0x{X:0>8}\n", .{ i, self.r[i], i_1, self.r[i_1], i_2, self.r[i_2], i_3, self.r[i_3] });
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}
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std.debug.print("cpsr: 0x{X:0>8} ", .{self.cpsr.raw});
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self.cpsr.toString();
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std.debug.print("spsr: 0x{X:0>8} ", .{self.spsr.raw});
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self.spsr.toString();
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std.debug.print("pipeline: {??X:0>8}\n", .{self.pipe.stage});
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if (self.cpsr.t.read()) {
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const opcode = self.bus.dbgRead(u16, self.r[15] - 4);
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const id = thumb.idx(opcode);
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std.debug.print("opcode: ID: 0x{b:0>10} 0x{X:0>4}\n", .{ id, opcode });
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} else {
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const opcode = self.bus.dbgRead(u32, self.r[15] - 4);
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const id = arm.idx(opcode);
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std.debug.print("opcode: ID: 0x{X:0>3} 0x{X:0>8}\n", .{ id, opcode });
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}
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std.debug.print("tick: {}\n\n", .{self.sched.now()});
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std.debug.panic(format, args);
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}
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pub fn interface(self: *Self) Interpreter {
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return switch (arch) {
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.v4t => .{ .v4t = self },
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.v5te => .{ .v5te = self },
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};
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}
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};
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}
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pub const Mode = enum(u5) {
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User = 0b10000,
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Fiq = 0b10001,
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Irq = 0b10010,
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Supervisor = 0b10011,
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Abort = 0b10111,
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Undefined = 0b11011,
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System = 0b11111,
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pub fn toString(self: Mode) []const u8 {
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return switch (self) {
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.User => "usr",
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.Fiq => "fiq",
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.Irq => "irq",
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.Supervisor => "svc",
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.Abort => "abt",
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.Undefined => "und",
|
||
|
|
.System => "sys",
|
||
|
|
};
|
||
|
|
}
|
||
|
|
|
||
|
|
fn get(bits: u5) ?Mode {
|
||
|
|
return std.meta.intToEnum(Mode, bits) catch null;
|
||
|
|
}
|
||
|
|
|
||
|
|
fn getChecked(cpu: anytype, bits: u5) Mode {
|
||
|
|
return get(bits) orelse cpu.panic("[CPU/CPSR] 0b{b:0>5} is an invalid CPU mode", .{bits});
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
pub const PSR = extern union {
|
||
|
|
mode: Bitfield(u32, 0, 5),
|
||
|
|
t: Bit(u32, 5),
|
||
|
|
f: Bit(u32, 6),
|
||
|
|
i: Bit(u32, 7),
|
||
|
|
v: Bit(u32, 28),
|
||
|
|
c: Bit(u32, 29),
|
||
|
|
z: Bit(u32, 30),
|
||
|
|
n: Bit(u32, 31),
|
||
|
|
raw: u32,
|
||
|
|
|
||
|
|
fn toString(self: @This()) void {
|
||
|
|
std.debug.print("[", .{});
|
||
|
|
|
||
|
|
if (self.n.read()) std.debug.print("N", .{}) else std.debug.print("-", .{});
|
||
|
|
if (self.z.read()) std.debug.print("Z", .{}) else std.debug.print("-", .{});
|
||
|
|
if (self.c.read()) std.debug.print("C", .{}) else std.debug.print("-", .{});
|
||
|
|
if (self.v.read()) std.debug.print("V", .{}) else std.debug.print("-", .{});
|
||
|
|
if (self.i.read()) std.debug.print("I", .{}) else std.debug.print("-", .{});
|
||
|
|
if (self.f.read()) std.debug.print("F", .{}) else std.debug.print("-", .{});
|
||
|
|
if (self.t.read()) std.debug.print("T", .{}) else std.debug.print("-", .{});
|
||
|
|
std.debug.print("|", .{});
|
||
|
|
if (Mode.get(self.mode.read())) |m| std.debug.print("{s}", .{m.toString()}) else std.debug.print("---", .{});
|
||
|
|
|
||
|
|
std.debug.print("]\n", .{});
|
||
|
|
}
|
||
|
|
|
||
|
|
pub inline fn check(self: @This(), cond: u4) bool {
|
||
|
|
const flags = @truncate(u4, self.raw >> 28);
|
||
|
|
|
||
|
|
return condition_lut[cond] & (@as(u16, 1) << flags) != 0;
|
||
|
|
}
|
||
|
|
};
|