From e1fec48a0e8ddf99a83bd99b5af4ad377bd5d440 Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Fri, 21 Oct 2022 05:12:07 -0300
Subject: [PATCH] fix(cpu): properly decode multiply instructions

---
 src/cpu.zig                               | 14 +++++++-------
 src/cpu/arm/half_signed_data_transfer.zig |  2 +-
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/cpu.zig b/src/cpu.zig
index 574e6f8..0374583 100644
--- a/src/cpu.zig
+++ b/src/cpu.zig
@@ -449,13 +449,6 @@ fn armPopulate() [0x1000]ArmInstrFn {
                 lut[i] = psrTransfer(I, R, kind);
             }
 
-            if (i >> 6 & 0x3F == 0b000000 and i & 0xF == 0b1001) {
-                const A = i >> 5 & 1 == 1;
-                const S = i >> 4 & 1 == 1;
-
-                lut[i] = multiply(A, S);
-            }
-
             if (i == 0x121) {
                 lut[i] = branchAndExchange;
             }
@@ -470,6 +463,13 @@ fn armPopulate() [0x1000]ArmInstrFn {
                 lut[i] = halfAndSignedDataTransfer(P, U, I, W, L);
             }
 
+            if (i >> 6 & 0x3F == 0b000000 and i & 0xF == 0b1001) {
+                const A = i >> 5 & 1 == 1;
+                const S = i >> 4 & 1 == 1;
+
+                lut[i] = multiply(A, S);
+            }
+
             if (i >> 10 & 0x3 == 0b01) {
                 const I = i >> 9 & 1 == 1;
                 const P = i >> 8 & 1 == 1;
diff --git a/src/cpu/arm/half_signed_data_transfer.zig b/src/cpu/arm/half_signed_data_transfer.zig
index 5661e55..264d0c1 100644
--- a/src/cpu/arm/half_signed_data_transfer.zig
+++ b/src/cpu/arm/half_signed_data_transfer.zig
@@ -58,7 +58,7 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
                     // STRH
                     bus.write16(address, @truncate(u16, cpu.r[rd]));
                 } else {
-                    std.debug.panic("[CPU] TODO: Figure out if this is also SWP", .{});
+                    std.debug.print("[CPU|ARM|SignedDataTransfer] {X:0>8} was improperly decoded", .{opcode});
                 }
             }