From e1f8400343c444b6e686b87aed2b7427968d42dd Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Fri, 21 Oct 2022 05:11:55 -0300
Subject: [PATCH] feat(cpu): stub PSR Transfer instructions

---
 src/cpu.zig              |  9 +++++++++
 src/cpu/psr_transfer.zig | 13 +++++++++++++
 2 files changed, 22 insertions(+)
 create mode 100644 src/cpu/psr_transfer.zig

diff --git a/src/cpu.zig b/src/cpu.zig
index 358bcc3..09bb9b1 100644
--- a/src/cpu.zig
+++ b/src/cpu.zig
@@ -8,6 +8,7 @@ const Bitfield = @import("bitfield").Bitfield;
 const Scheduler = @import("scheduler.zig").Scheduler;
 
 const dataProcessing = @import("cpu/data_processing.zig").dataProcessing;
+const psrTransfer = @import("cpu/psr_transfer.zig").psrTransfer;
 const singleDataTransfer = @import("cpu/single_data_transfer.zig").singleDataTransfer;
 const halfAndSignedDataTransfer = @import("cpu/half_signed_data_transfer.zig").halfAndSignedDataTransfer;
 const blockDataTransfer = @import("cpu/block_data_transfer.zig").blockDataTransfer;
@@ -133,6 +134,14 @@ fn populate() [0x1000]InstrFn {
                 lut[i] = dataProcessing(I, S, instrKind);
             }
 
+            if (i >> 10 & 0x3 == 0b00 and i >> 7 & 0x3 == 0b10 and i >> 4 & 1 == 0) {
+                // PSR Transfer
+                const I = i >> 9 & 1 == 1;
+                const isSpsr = i >> 6 & 1 == 1;
+
+                lut[i] = psrTransfer(I, isSpsr);
+            }
+
             if (i >> 9 & 0x7 == 0b000 and i >> 3 & 1 == 1 and i & 1 == 1) {
                 const P = i >> 8 & 1 == 1;
                 const U = i >> 7 & 1 == 1;
diff --git a/src/cpu/psr_transfer.zig b/src/cpu/psr_transfer.zig
new file mode 100644
index 0000000..1e5aab2
--- /dev/null
+++ b/src/cpu/psr_transfer.zig
@@ -0,0 +1,13 @@
+const std = @import("std");
+
+const Bus = @import("../Bus.zig");
+const Arm7tdmi = @import("../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../cpu.zig").InstrFn;
+
+pub fn psrTransfer(comptime _: bool, comptime _: bool) InstrFn {
+    return struct {
+        fn inner(_: *Arm7tdmi, _: *Bus, _: u32) void {
+            std.debug.panic("[CPU] TODO: Implement PSR Transfer Instructions", .{});
+        }
+    }.inner;
+}