From d72f85c27449c5a492eb0e5569cffc41b986b29e Mon Sep 17 00:00:00 2001 From: Rekai Musuka Date: Sun, 20 Feb 2022 18:40:22 -0500 Subject: [PATCH] feat: implement Hblank and Vcount Interrupts Also implemented unique behaviour when writing to IF --- src/bus/io.zig | 2 +- src/cpu.zig | 36 ++++++++++++++++++++++++++++-------- src/scheduler.zig | 29 ++++++++++++++++++++++++++--- 3 files changed, 55 insertions(+), 12 deletions(-) diff --git a/src/bus/io.zig b/src/bus/io.zig index d5c2b6b..9e6a005 100644 --- a/src/bus/io.zig +++ b/src/bus/io.zig @@ -105,7 +105,7 @@ pub fn write16(bus: *Bus, addr: u32, halfword: u16) void { 0x0400_001C => bus.ppu.bg[3].hofs.raw = halfword, 0x0400_001E => bus.ppu.bg[3].vofs.raw = halfword, 0x0400_0200 => bus.io.ie.raw = halfword, - 0x0400_0202 => bus.io.irq.raw = halfword, + 0x0400_0202 => bus.io.irq.raw &= ~halfword, 0x0400_0208 => bus.io.ime = halfword & 1 == 1, else => std.debug.panic("Tried to write 0x{X:0>4} to 0x{X:0>8}", .{ halfword, addr }), } diff --git a/src/cpu.zig b/src/cpu.zig index 15edf18..3c16aff 100644 --- a/src/cpu.zig +++ b/src/cpu.zig @@ -246,14 +246,8 @@ pub const Arm7tdmi = struct { } pub fn step(self: *Self) u64 { - if (self.bus.io.is_halted) { - // const ie = self.bus.io.ie.raw; - // const irq = self.bus.io.irq.raw; - - // if (ie & irq != 0) self.bus.io.is_halted = false; - - // log.warn("FIXME: Enable GBA HALTing", .{}); - } + // If we're halted, the cpu is disabled + if (self.bus.io.is_halted) return 1; if (self.cpsr.t.read()) { const opcode = self.thumbFetch(); @@ -272,6 +266,32 @@ pub const Arm7tdmi = struct { return 1; } + pub fn handleInterrupt(self: *Self) void { + const should_handle = self.bus.io.ie.raw & self.bus.io.irq.raw; + + if (should_handle != 0) { + self.bus.io.is_halted = false; + // log.info("An Interrupt was Fired!", .{}); + + // Either IME is not true or I in CPSR is true + // Don't handle interrupts + if (!self.bus.io.ime or self.cpsr.i.read()) return; + // log.info("An interrupt was Handled!", .{}); + + // TODO: Should this behave like Software Interrupts? + const r15 = self.r[15] - 4; + const cpsr = self.cpsr.raw; + + self.changeMode(.Irq); + self.cpsr.t.write(false); + self.cpsr.i.write(true); + + self.r[14] = r15; + self.spsr.raw = cpsr; + self.r[15] = 0x000_0018; + } + } + fn thumbFetch(self: *Self) u16 { const halfword = self.bus.read16(self.r[15]); self.r[15] += 2; diff --git a/src/scheduler.zig b/src/scheduler.zig index ec161bb..c62c073 100644 --- a/src/scheduler.zig +++ b/src/scheduler.zig @@ -25,7 +25,7 @@ pub const Scheduler = struct { self.queue.deinit(); } - pub fn handleEvent(self: *Self, _: *Arm7tdmi, bus: *Bus) void { + pub fn handleEvent(self: *Self, cpu: *Arm7tdmi, bus: *Bus) void { const should_handle = if (self.queue.peek()) |e| self.tick >= e.tick else false; if (should_handle) { @@ -37,19 +37,42 @@ pub const Scheduler = struct { std.debug.panic("[Scheduler] Somehow, a u64 overflowed", .{}); }, .HBlank => { + const dispstat = &bus.ppu.dispstat; + // The End of a Hblank (During Draw or Vblank) const old_scanline = bus.ppu.vcount.scanline.read(); const scanline = (old_scanline + 1) % 228; bus.ppu.vcount.scanline.write(scanline); - bus.ppu.dispstat.hblank.unset(); + dispstat.hblank.unset(); + + // Fire Hblank Interrupt @ the end of Hblank Draw + if (dispstat.hblank_irq.read()) { + bus.io.irq.hblank.set(); + cpu.handleInterrupt(); + } if (scanline < 160) { // Transitioning to another Draw + + if (scanline == dispstat.vcount_trigger.read()) { + dispstat.coincidence.set(); + if (dispstat.vcount_irq.read()) { + bus.io.irq.coincidence.set(); + cpu.handleInterrupt(); + } + } + self.push(.Draw, self.tick + (240 * 4)); } else { + // Transitioning to a Vblank - if (scanline < 227) bus.ppu.dispstat.vblank.set() else bus.ppu.dispstat.vblank.unset(); + if (scanline == 160) { + bus.io.irq.vblank.set(); + cpu.handleInterrupt(); + } + + if (scanline < 227) dispstat.vblank.set() else dispstat.vblank.unset(); self.push(.VBlank, self.tick + (240 * 4)); }