From d495f5b4c58dff7c7082f46dc7b09c785aa3906a Mon Sep 17 00:00:00 2001 From: Rekai Musuka Date: Fri, 21 Oct 2022 05:11:49 -0300 Subject: [PATCH] feat: implement S (when rd != 15) for several data processing instructions --- src/cpu/barrel_shifter.zig | 24 +++++++++---- src/cpu/data_processing.zig | 59 +++++++++++++++----------------- src/cpu/single_data_transfer.zig | 11 +++--- 3 files changed, 52 insertions(+), 42 deletions(-) diff --git a/src/cpu/barrel_shifter.zig b/src/cpu/barrel_shifter.zig index 1e8c9fb..6a935f6 100644 --- a/src/cpu/barrel_shifter.zig +++ b/src/cpu/barrel_shifter.zig @@ -4,7 +4,7 @@ const arm = @import("../cpu.zig"); const Arm7tdmi = arm.Arm7tdmi; const CPSR = arm.CPSR; -pub inline fn exec(cpu: *Arm7tdmi, opcode: u32) u32 { +pub inline fn exec(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 { var shift_amt: u8 = undefined; if (opcode >> 4 & 1 == 1) { shift_amt = @truncate(u8, cpu.r[opcode >> 8 & 0xF]); @@ -14,12 +14,22 @@ pub inline fn exec(cpu: *Arm7tdmi, opcode: u32) u32 { const rm = cpu.r[opcode & 0xF]; - return switch (@truncate(u2, opcode >> 5)) { - 0b00 => logical_left(&cpu.cpsr, rm, shift_amt), - 0b01 => logical_right(&cpu.cpsr, rm, shift_amt), - 0b10 => arithmetic_right(&cpu.cpsr, rm, shift_amt), - 0b11 => rotate_right(&cpu.cpsr, rm, shift_amt), - }; + if (S) { + return switch (@truncate(u2, opcode >> 5)) { + 0b00 => logical_left(&cpu.cpsr, rm, shift_amt), + 0b01 => logical_right(&cpu.cpsr, rm, shift_amt), + 0b10 => arithmetic_right(&cpu.cpsr, rm, shift_amt), + 0b11 => rotate_right(&cpu.cpsr, rm, shift_amt), + }; + } else { + var dummy = CPSR{ .raw = 0x0000_0000 }; + return switch (@truncate(u2, opcode >> 5)) { + 0b00 => logical_left(&dummy, rm, shift_amt), + 0b01 => logical_right(&dummy, rm, shift_amt), + 0b10 => arithmetic_right(&dummy, rm, shift_amt), + 0b11 => rotate_right(&dummy, rm, shift_amt), + }; + } } pub inline fn logical_left(cpsr: *CPSR, rm: u32, shift_byte: u8) u32 { diff --git a/src/cpu/data_processing.zig b/src/cpu/data_processing.zig index 1f73716..41173ae 100644 --- a/src/cpu/data_processing.zig +++ b/src/cpu/data_processing.zig @@ -16,60 +16,57 @@ pub fn comptimeDataProcessing(comptime I: bool, comptime S: bool, comptime instr if (I) { op2 = std.math.rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) << 1); } else { - op2 = BarrelShifter.exec(cpu, opcode); + if (S and rd == 0xF) { + std.debug.panic("[CPU] Data Processing Instruction w/ S set and Rd == 15", .{}); + } else { + op2 = BarrelShifter.exec(S, cpu, opcode); + } } switch (instrKind) { 0x4 => { // ADD - cpu.r[rd] = cpu.r[op1] + op2; + var result: u32 = undefined; + const didOverflow = @addWithOverflow(u32, cpu.r[op1], op2, &result); + cpu.r[rd] = result; - if (S) std.debug.panic("[CPU] TODO: implement ADD condition codes", .{}); + if (S and rd != 0xF) { + cpu.cpsr.n.write(result >> 31 & 1 == 1); + cpu.cpsr.z.write(result == 0); + cpu.cpsr.c.write(didOverflow); + cpu.cpsr.v.write(((op1 ^ result) & (op2 ^ result)) >> 31 & 1 == 1); + } }, 0x8 => { // TST - std.debug.panic("[CPU] TODO: implement TST, also figure out barrel shifter flags\n", .{}); + const result = cpu.r[op1] & op2; + + cpu.cpsr.n.write(result >> 31 & 1 == 1); + cpu.cpsr.z.write(result == 0); + // Barrel Shifter should always calc CPSR C in TST + if (!S) _ = BarrelShifter.exec(true, cpu, opcode); }, 0xD => { // MOV cpu.r[rd] = op2; - if (S) std.debug.panic("[CPU] implement MOV condition codes", .{}); + if (S and rd != 0xF) { + cpu.cpsr.n.write(op2 >> 31 & 1 == 1); + cpu.cpsr.z.write(op2 == 0); + // C set by Barr0x15el Shifter, V is unnafected + } }, 0xA => { // CMP - const op1_val = cpu.r[op1]; - const v_ctx = (op1_val >> 31 == 1) or (op2 >> 31 == 1); - - const result = op1_val -% op2; + const result = cpu.r[op1] -% op2; cpu.cpsr.n.write(result >> 31 & 1 == 1); cpu.cpsr.z.write(result == 0); - cpu.cpsr.c.write(op2 <= op1_val); - cpu.cpsr.v.write(v_ctx and (result >> 31 & 1 == 1)); + cpu.cpsr.c.write(op2 <= cpu.r[op1]); + cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1); }, else => std.debug.panic("[CPU] TODO: implement data processing type {}", .{instrKind}), } } }.dataProcessing; } - -// fn registerOp2(cpu: *const Arm7tdmi, opcode: u32) u32 { -// var amount: u32 = undefined; -// if (opcode >> 4 & 0x01 == 0x01) { -// amount = cpu.r[opcode >> 8 & 0xF] & 0xFF; -// } else { -// amount = opcode >> 7 & 0x1F; -// } - -// const rm = opcode & 0xF; -// const r_val = cpu.r[rm]; - -// return switch (opcode >> 5 & 0x03) { -// 0b00 => r_val << @truncate(u5, amount), -// 0b01 => r_val >> @truncate(u5, amount), -// 0b10 => @bitCast(u32, @bitCast(i32, r_val) >> @truncate(u5, amount)), -// 0b11 => std.math.rotr(u32, r_val, amount), -// else => unreachable, -// }; -// } diff --git a/src/cpu/single_data_transfer.zig b/src/cpu/single_data_transfer.zig index c30bb00..2f9a54f 100644 --- a/src/cpu/single_data_transfer.zig +++ b/src/cpu/single_data_transfer.zig @@ -6,6 +6,7 @@ const BarrelShifter = @import("barrel_shifter.zig"); const Bus = @import("../bus.zig").Bus; const Arm7tdmi = arm.Arm7tdmi; const InstrFn = arm.InstrFn; +const CPSR = arm.CPSR; pub fn comptimeSingleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool, comptime B: bool, comptime W: bool, comptime L: bool) InstrFn { return struct { @@ -53,10 +54,12 @@ fn registerOffset(cpu: *Arm7tdmi, opcode: u32) u32 { const rm = cpu.r[opcode & 0xF]; + var dummy = CPSR{ .raw = 0x0000_0000 }; + return switch (@truncate(u2, opcode >> 5)) { - 0b00 => BarrelShifter.logical_left(&cpu.cpsr, rm, shift_byte), - 0b01 => BarrelShifter.logical_right(&cpu.cpsr, rm, shift_byte), - 0b10 => BarrelShifter.arithmetic_right(&cpu.cpsr, rm, shift_byte), - 0b11 => BarrelShifter.rotate_right(&cpu.cpsr, rm, shift_byte), + 0b00 => BarrelShifter.logical_left(&dummy, rm, shift_byte), + 0b01 => BarrelShifter.logical_right(&dummy, rm, shift_byte), + 0b10 => BarrelShifter.arithmetic_right(&dummy, rm, shift_byte), + 0b11 => BarrelShifter.rotate_right(&dummy, rm, shift_byte), }; }