From d2740e30d91344122fa76f9c068c9e5d843af93b Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Sun, 13 Feb 2022 00:34:47 -0400
Subject: [PATCH] chore: squash bugs preventing swi_demo.gba from working

---
 src/cpu/thumb/branch.zig            | 2 +-
 src/cpu/thumb/data_transfer.zig     | 2 +-
 src/cpu/thumb/processing_branch.zig | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/cpu/thumb/branch.zig b/src/cpu/thumb/branch.zig
index 58cbaff..d8f3107 100644
--- a/src/cpu/thumb/branch.zig
+++ b/src/cpu/thumb/branch.zig
@@ -43,7 +43,7 @@ pub fn format19(comptime is_low: bool) InstrFn {
                 // Instruction 2
                 const old_pc = cpu.r[15];
 
-                cpu.r[15] = cpu.r[14] + (offset << 1);
+                cpu.r[15] = cpu.r[14] +% (offset << 1);
                 cpu.r[14] = old_pc | 1;
             } else {
                 // Instruction 1
diff --git a/src/cpu/thumb/data_transfer.zig b/src/cpu/thumb/data_transfer.zig
index 15ed733..5c2bda0 100644
--- a/src/cpu/thumb/data_transfer.zig
+++ b/src/cpu/thumb/data_transfer.zig
@@ -116,7 +116,7 @@ pub fn format10(comptime L: bool, comptime offset: u5) InstrFn {
             const rb = opcode >> 3 & 0x7;
             const rd = opcode & 0x7;
 
-            const address = cpu.r[rb] + (offset << 1);
+            const address = cpu.r[rb] + (@as(u6, offset) << 1);
 
             if (L) {
                 // LDRH
diff --git a/src/cpu/thumb/processing_branch.zig b/src/cpu/thumb/processing_branch.zig
index 0540526..c30d7e4 100644
--- a/src/cpu/thumb/processing_branch.zig
+++ b/src/cpu/thumb/processing_branch.zig
@@ -18,12 +18,12 @@ pub fn format5(comptime op: u2, comptime h1: u1, comptime h2: u1) InstrFn {
                 0b00 => {
                     // ADD
                     const sum = add(false, cpu, dst, src);
-                    cpu.r[dst_idx] = if (dst_idx == 0xF) sum & 0xFFFF_FFFC else sum;
+                    cpu.r[dst_idx] = if (dst_idx == 0xF) sum & 0xFFFF_FFFE else sum;
                 },
                 0b01 => cmp(cpu, dst, src), // CMP
                 0b10 => {
                     // MOV
-                    cpu.r[dst_idx] = if (dst_idx == 0xF) src & 0xFFFF_FFFC else src;
+                    cpu.r[dst_idx] = if (dst_idx == 0xF) src & 0xFFFF_FFFE else src;
                 },
                 0b11 => {
                     // BX