From cf38dee61acd65619dfde037060ce6d6c9e3e759 Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Sat, 2 Jul 2022 10:09:25 -0300
Subject: [PATCH] feat: fake the pipeline less

---
 src/cpu/arm/block_data_transfer.zig | 10 ++++++++--
 src/cpu/barrel_shifter.zig          |  8 ++------
 src/cpu/thumb/branch.zig            |  4 ++--
 3 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/src/cpu/arm/block_data_transfer.zig b/src/cpu/arm/block_data_transfer.zig
index 7946a75..09e74c7 100644
--- a/src/cpu/arm/block_data_transfer.zig
+++ b/src/cpu/arm/block_data_transfer.zig
@@ -86,8 +86,14 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
                     cpu.setUserModeRegister(i, bus.read(u32, address));
                 } else {
                     const value = bus.read(u32, address);
-                    cpu.r[i] = if (i == 0xF) value & 0xFFFF_FFFC else value;
-                    if (S and i == 0xF) cpu.setCpsr(cpu.spsr.raw);
+
+                    cpu.r[i] = value;
+                    if (i == 0xF) {
+                        cpu.r[i] &= ~@as(u32, 3); // Align r15
+                        cpu.pipe.flush();
+
+                        if (S) cpu.setCpsr(cpu.spsr.raw);
+                    }
                 }
             } else {
                 if (S) {
diff --git a/src/cpu/barrel_shifter.zig b/src/cpu/barrel_shifter.zig
index 7b2c1b8..fa648b5 100644
--- a/src/cpu/barrel_shifter.zig
+++ b/src/cpu/barrel_shifter.zig
@@ -18,11 +18,9 @@ pub fn execute(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
 
 fn registerShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
     const rs_idx = opcode >> 8 & 0xF;
+    const rm = cpu.r[opcode & 0xF];
     const rs = @truncate(u8, cpu.r[rs_idx]);
 
-    const rm_idx = opcode & 0xF;
-    const rm = if (rm_idx == 0xF) cpu.fakePC() else cpu.r[rm_idx];
-
     return switch (@truncate(u2, opcode >> 5)) {
         0b00 => logicalLeft(S, &cpu.cpsr, rm, rs),
         0b01 => logicalRight(S, &cpu.cpsr, rm, rs),
@@ -33,9 +31,7 @@ fn registerShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
 
 pub fn immShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 {
     const amount = @truncate(u8, opcode >> 7 & 0x1F);
-
-    const rm_idx = opcode & 0xF;
-    const rm = if (rm_idx == 0xF) cpu.fakePC() else cpu.r[rm_idx];
+    const rm = cpu.r[opcode & 0xF];
 
     var result: u32 = undefined;
     if (amount == 0) {
diff --git a/src/cpu/thumb/branch.zig b/src/cpu/thumb/branch.zig
index 63d6478..6644f6c 100644
--- a/src/cpu/thumb/branch.zig
+++ b/src/cpu/thumb/branch.zig
@@ -24,8 +24,8 @@ pub fn format18() InstrFn {
     return struct {
         // B but conditional
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
-            const offset = sext(u32, u11, opcode & 0x7FF) << 1;
-            cpu.r[15] = (cpu.r[15] + 2) +% offset;
+            cpu.r[15] +%= sext(u32, u11, opcode & 0x7FF) << 1;
+            cpu.pipe.flush();
         }
     }.inner;
 }