diff --git a/src/core/bus/dma.zig b/src/core/bus/dma.zig
index 0d25bd0..d08a871 100644
--- a/src/core/bus/dma.zig
+++ b/src/core/bus/dma.zig
@@ -11,6 +11,8 @@ const log = std.log.scoped(.DmaTransfer);
 const setHi = util.setHi;
 const setLo = util.setLo;
 
+const rotr = @import("../../util.zig").rotr;
+
 pub fn create() DmaTuple {
     return .{ DmaController(0).init(), DmaController(1).init(), DmaController(2).init(), DmaController(3).init() };
 }
@@ -112,6 +114,8 @@ fn DmaController(comptime id: u2) type {
         /// Note: Use writeControl instead of manipulating cnt directly.
         cnt: DmaControl,
 
+        /// Internal. The last successfully read value
+        data_latch: u32,
         /// Internal. Currrent Source Address
         sad_latch: u32,
         /// Internal. Current Destination Address
@@ -134,6 +138,8 @@ fn DmaController(comptime id: u2) type {
                 // Internals
                 .sad_latch = 0,
                 .dad_latch = 0,
+                .data_latch = 0,
+
                 ._word_count = 0,
                 .in_progress = false,
             };
@@ -182,10 +188,12 @@ fn DmaController(comptime id: u2) type {
 
             const mask = if (transfer_type) ~@as(u32, 3) else ~@as(u32, 1);
 
+            if (self.sad_latch & mask >= 0x0200_0000) self.data_latch = cpu.bus.read(u32, self.sad_latch & mask);
+
             if (transfer_type) {
-                cpu.bus.write(u32, self.dad_latch & mask, cpu.bus.read(u32, self.sad_latch & mask));
+                cpu.bus.write(u32, self.dad_latch & mask, self.data_latch);
             } else {
-                cpu.bus.write(u16, self.dad_latch & mask, cpu.bus.read(u16, self.sad_latch & mask));
+                cpu.bus.write(u16, self.dad_latch & mask, @truncate(u16, rotr(u32, self.data_latch, 8 * (self.dad_latch & 3))));
             }
 
             switch (sad_adj) {