diff --git a/src/bus/dma.zig b/src/bus/dma.zig index 0e741ca..3283a1b 100644 --- a/src/bus/dma.zig +++ b/src/bus/dma.zig @@ -85,7 +85,6 @@ pub fn DmaController(comptime id: u2) type { const dad_adj = std.meta.intToEnum(Adjustment, self.cnt.dad_adj.read()) catch unreachable; var offset: u32 = 0; - if (self.cnt.transfer_type.read()) { offset = @sizeOf(u32); // 32-bit Transfer const word = bus.read32(self._sad); diff --git a/src/cpu/arm/branch.zig b/src/cpu/arm/branch.zig index 39365f5..362366a 100644 --- a/src/cpu/arm/branch.zig +++ b/src/cpu/arm/branch.zig @@ -4,13 +4,13 @@ const Bus = @import("../../Bus.zig"); const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const InstrFn = @import("../../cpu.zig").ArmInstrFn; -const u32SignExtend = @import("../../util.zig").u32SignExtend; +const sext = @import("../../util.zig").sext; pub fn branch(comptime L: bool) InstrFn { return struct { fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void { if (L) cpu.r[14] = cpu.r[15]; - cpu.r[15] = cpu.fakePC() +% u32SignExtend(24, opcode << 2); + cpu.r[15] = cpu.fakePC() +% sext(24, opcode << 2); } }.inner; } diff --git a/src/cpu/arm/half_signed_data_transfer.zig b/src/cpu/arm/half_signed_data_transfer.zig index b089adb..fd3ee58 100644 --- a/src/cpu/arm/half_signed_data_transfer.zig +++ b/src/cpu/arm/half_signed_data_transfer.zig @@ -4,7 +4,7 @@ const Bus = @import("../../Bus.zig"); const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const InstrFn = @import("../../cpu.zig").ArmInstrFn; -const u32SignExtend = @import("../../util.zig").u32SignExtend; +const sext = @import("../../util.zig").sext; pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn { return struct { @@ -42,14 +42,14 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I: }, 0b10 => { // LDRSB - result = u32SignExtend(8, bus.read8(address)); + result = sext(8, bus.read8(address)); }, 0b11 => { // LDRSH const value = if (address & 1 == 1) blk: { - break :blk u32SignExtend(8, bus.read8(address)); + break :blk sext(8, bus.read8(address)); } else blk: { - break :blk u32SignExtend(16, bus.read16(address)); + break :blk sext(16, bus.read16(address)); }; result = std.math.rotr(u32, value, 8 * (address & 1)); diff --git a/src/cpu/thumb/branch.zig b/src/cpu/thumb/branch.zig index d747f19..3bc8277 100644 --- a/src/cpu/thumb/branch.zig +++ b/src/cpu/thumb/branch.zig @@ -3,13 +3,13 @@ const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const InstrFn = @import("../../cpu.zig").ThumbInstrFn; const checkCond = @import("../../cpu.zig").checkCond; -const u32SignExtend = @import("../../util.zig").u32SignExtend; +const sext = @import("../../util.zig").sext; pub fn format16(comptime cond: u4) InstrFn { return struct { fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void { // B - const offset = u32SignExtend(8, opcode & 0xFF) << 1; + const offset = sext(8, opcode & 0xFF) << 1; const should_execute = switch (cond) { 0xE, 0xF => cpu.panic("[CPU/THUMB.16] Undefined conditional branch with condition {}", .{cond}), @@ -27,7 +27,7 @@ pub fn format18() InstrFn { return struct { // B but conditional fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void { - const offset = u32SignExtend(11, opcode & 0x7FF) << 1; + const offset = sext(11, opcode & 0x7FF) << 1; cpu.r[15] = (cpu.r[15] + 2) +% offset; } }.inner; @@ -47,7 +47,7 @@ pub fn format19(comptime is_low: bool) InstrFn { cpu.r[14] = old_pc | 1; } else { // Instruction 1 - cpu.r[14] = (cpu.r[15] + 2) +% (u32SignExtend(11, offset) << 12); + cpu.r[14] = (cpu.r[15] + 2) +% (sext(11, offset) << 12); } } }.inner; diff --git a/src/cpu/thumb/data_transfer.zig b/src/cpu/thumb/data_transfer.zig index 5c2bda0..9807df7 100644 --- a/src/cpu/thumb/data_transfer.zig +++ b/src/cpu/thumb/data_transfer.zig @@ -14,7 +14,7 @@ pub fn format6(comptime rd: u3) InstrFn { }.inner; } -const u32SignExtend = @import("../../util.zig").u32SignExtend; +const sext = @import("../../util.zig").sext; pub fn format78(comptime op: u2, comptime T: bool) InstrFn { return struct { @@ -34,7 +34,7 @@ pub fn format78(comptime op: u2, comptime T: bool) InstrFn { }, 0b01 => { // LDSB - cpu.r[rd] = u32SignExtend(8, bus.read8(address)); + cpu.r[rd] = sext(8, bus.read8(address)); }, 0b10 => { // LDRH @@ -44,9 +44,9 @@ pub fn format78(comptime op: u2, comptime T: bool) InstrFn { 0b11 => { // LDRSH const value = if (address & 1 == 1) blk: { - break :blk u32SignExtend(8, bus.read8(address)); + break :blk sext(8, bus.read8(address)); } else blk: { - break :blk u32SignExtend(16, bus.read16(address)); + break :blk sext(16, bus.read16(address)); }; cpu.r[rd] = std.math.rotr(u32, value, 8 * (address & 1)); diff --git a/src/util.zig b/src/util.zig index 2b74378..2a4bc6d 100644 --- a/src/util.zig +++ b/src/util.zig @@ -1,29 +1,8 @@ const std = @import("std"); -pub fn u32SignExtend(comptime bits: usize, value: u32) u32 { - return @bitCast(u32, signExtend(i32, bits, @bitCast(i32, value))); -} - -fn signExtend(comptime T: type, comptime bits: usize, value: anytype) T { - const ValT = comptime @TypeOf(value); - comptime std.debug.assert(isInteger(ValT)); - comptime std.debug.assert(isSigned(ValT)); - - const value_bits = @typeInfo(ValT).Int.bits; - comptime std.debug.assert(value_bits >= bits); - - const bit_diff = value_bits - bits; - - // (1 << bits) -1 is a mask that will take values like 0x100 and make them 0xFF - // value & mask so that only the relevant bits are sign extended - // therefore, value & ((1 << bits) - 1) is the isolation of the relevant bits - return ((value & ((1 << bits) - 1)) << bit_diff) >> bit_diff; -} - -fn isInteger(comptime T: type) bool { - return @typeInfo(T) == .Int; -} - -fn isSigned(comptime T: type) bool { - return @typeInfo(T).Int.signedness == .signed; +pub fn sext(comptime bits: comptime_int, value: u32) u32 { + comptime std.debug.assert(bits <= 32); + const amount = 32 - bits; + + return @bitCast(u32, @bitCast(i32, value << amount) >> amount); }