From c93153672fe7a320e124b17f4cb7da54a2028bde Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Fri, 21 Oct 2022 05:11:59 -0300
Subject: [PATCH] feat(cpu): implement ADD

---
 src/cpu/arm/data_processing.zig | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/cpu/arm/data_processing.zig b/src/cpu/arm/data_processing.zig
index 0370076..5c167d9 100644
--- a/src/cpu/arm/data_processing.zig
+++ b/src/cpu/arm/data_processing.zig
@@ -23,6 +23,16 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
             }
 
             switch (instrKind) {
+                0x0 => {
+                    const result = op1 & op2;
+                    cpu.r[rd] = result;
+
+                    if (S and rd != 0xF) {
+                        cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                        cpu.cpsr.z.write(result == 0);
+                        // C set by Barrel Shifter, V is unaffected
+                    }
+                },
                 0x2 => {
                     // SUB
                     const result = op1 -% op2;