From b9a81baa47e1dda9740938c726fedb9b42edf77e Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Fri, 21 Oct 2022 05:12:06 -0300
Subject: [PATCH] feat(cpu): implement THUMB ldmia stmia

---
 src/cpu.zig                |  8 ++++++++
 src/cpu/thumb/format15.zig | 29 +++++++++++++++++++++++++++++
 2 files changed, 37 insertions(+)
 create mode 100644 src/cpu/thumb/format15.zig

diff --git a/src/cpu.zig b/src/cpu.zig
index ad1ff43..21d495f 100644
--- a/src/cpu.zig
+++ b/src/cpu.zig
@@ -26,6 +26,7 @@ const format2 = @import("cpu/thumb/format2.zig").format2;
 const format5 = @import("cpu/thumb/format5.zig").format5;
 const format6 = @import("cpu/thumb/format6.zig").format6;
 const format12 = @import("cpu/thumb/format12.zig").format12;
+const format15 = @import("cpu/thumb/format15.zig").format15;
 const format16 = @import("cpu/thumb/format16.zig").format16;
 const format19 = @import("cpu/thumb/format19.zig").format19;
 
@@ -375,6 +376,13 @@ fn thumbPopulate() [0x400]ThumbInstrFn {
                 lut[i] = format12(isSP, rd);
             }
 
+            if (i >> 6 & 0xF == 0b1100) {
+                const L = i >> 5 & 1 == 1;
+                const rb = i >> 2 & 0x3;
+
+                lut[i] = format15(L, rb);
+            }
+
             if (i >> 6 & 0xF == 0b1101) {
                 const cond = i >> 2 & 0xF;
 
diff --git a/src/cpu/thumb/format15.zig b/src/cpu/thumb/format15.zig
new file mode 100644
index 0000000..ec7559f
--- /dev/null
+++ b/src/cpu/thumb/format15.zig
@@ -0,0 +1,29 @@
+const std = @import("std");
+
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
+
+pub fn format15(comptime L: bool, comptime rb: u3) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void {
+            const base = cpu.r[rb];
+
+            var address: u32 = base;
+
+            var i: usize = 0;
+            while (i < 8) : (i += 1) {
+                if ((opcode >> @truncate(u3, i)) & 1 == 1) {
+                    if (L) {
+                        cpu.r[i] = bus.read32(address);
+                    } else {
+                        bus.write32(address, cpu.r[i]);
+                    }
+                    address += 4;
+                }
+            }
+
+            cpu.r[rb] = address;
+        }
+    }.inner;
+}