diff --git a/src/core/bus/dma.zig b/src/core/bus/dma.zig index 0d25bd0..8534871 100644 --- a/src/core/bus/dma.zig +++ b/src/core/bus/dma.zig @@ -11,6 +11,8 @@ const log = std.log.scoped(.DmaTransfer); const setHi = util.setHi; const setLo = util.setLo; +const rotr = @import("../../util.zig").rotr; + pub fn create() DmaTuple { return .{ DmaController(0).init(), DmaController(1).init(), DmaController(2).init(), DmaController(3).init() }; } @@ -112,6 +114,8 @@ fn DmaController(comptime id: u2) type { /// Note: Use writeControl instead of manipulating cnt directly. cnt: DmaControl, + /// Internal. The last successfully read value + data_latch: u32, /// Internal. Currrent Source Address sad_latch: u32, /// Internal. Current Destination Address @@ -134,6 +138,8 @@ fn DmaController(comptime id: u2) type { // Internals .sad_latch = 0, .dad_latch = 0, + .data_latch = 0, + ._word_count = 0, .in_progress = false, }; @@ -181,11 +187,15 @@ fn DmaController(comptime id: u2) type { const offset: u32 = if (transfer_type) @sizeOf(u32) else @sizeOf(u16); const mask = if (transfer_type) ~@as(u32, 3) else ~@as(u32, 1); + const sad_addr = self.sad_latch & mask; + const dad_addr = self.dad_latch & mask; if (transfer_type) { - cpu.bus.write(u32, self.dad_latch & mask, cpu.bus.read(u32, self.sad_latch & mask)); + if (sad_addr > 0x0200_0000) self.data_latch = cpu.bus.read(u32, sad_addr); + cpu.bus.write(u32, dad_addr, self.data_latch); } else { - cpu.bus.write(u16, self.dad_latch & mask, cpu.bus.read(u16, self.sad_latch & mask)); + if (sad_addr > 0x0200_0000) self.data_latch = cpu.bus.read(u16, sad_addr); + cpu.bus.write(u16, dad_addr, @truncate(u16, rotr(u32, self.data_latch, 8 * (dad_addr & 3)))); } switch (sad_adj) {