From b3b8182f85f4ef96b40abc304137655955374ad7 Mon Sep 17 00:00:00 2001 From: Rekai Musuka Date: Fri, 21 Oct 2022 05:12:01 -0300 Subject: [PATCH] fix(cpu): fix PC offset when barrel shifter and bit 4 of DP is set --- src/cpu/arm/barrel_shifter.zig | 2 +- src/cpu/arm/data_processing.zig | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/cpu/arm/barrel_shifter.zig b/src/cpu/arm/barrel_shifter.zig index b9e5e88..22b5f6d 100644 --- a/src/cpu/arm/barrel_shifter.zig +++ b/src/cpu/arm/barrel_shifter.zig @@ -19,7 +19,7 @@ fn registerShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 { const rs = @truncate(u8, cpu.r[rs_idx]); const rm_idx = opcode & 0xF; - const rm = if (rm_idx == 0xF) cpu.fakePC() + 4 else cpu.r[rm_idx]; + const rm = if (rm_idx == 0xF) cpu.fakePC() else cpu.r[rm_idx]; return switch (@truncate(u2, opcode >> 5)) { 0b00 => logicalLeft(S, &cpu.cpsr, rm, rs), diff --git a/src/cpu/arm/data_processing.zig b/src/cpu/arm/data_processing.zig index 92192e7..078ce47 100644 --- a/src/cpu/arm/data_processing.zig +++ b/src/cpu/arm/data_processing.zig @@ -12,6 +12,9 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4 const rn = opcode >> 16 & 0xF; const old_carry = @boolToInt(cpu.cpsr.c.read()); + // If certain conditions are met, PC is 12 ahead instead of 8 + if (!I and opcode >> 4 & 1 == 1) cpu.r[15] += 4; + const op1 = if (rn == 0xF) cpu.fakePC() else cpu.r[rn]; var op2: u32 = undefined; @@ -22,6 +25,9 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4 op2 = shifter.execute(S, cpu, opcode); } + // Undo special condition from above + if (!I and opcode >> 4 & 1 == 1) cpu.r[15] -= 4; + switch (instrKind) { 0x0 => { // AND