From 9cce4d98595cd16f339915006a79abfb2b0dbfef Mon Sep 17 00:00:00 2001 From: Rekai Musuka Date: Thu, 21 Apr 2022 10:15:52 -0300 Subject: [PATCH] chore: misc improvements --- src/Bus.zig | 15 +------ src/apu.zig | 10 ++--- src/bus/Bios.zig | 4 +- src/bus/backup.zig | 2 +- src/bus/dma.zig | 7 --- src/bus/io.zig | 84 ++++++++++++++++++------------------ src/cpu.zig | 19 ++++---- src/cpu/arm/psr_transfer.zig | 4 +- src/emu.zig | 10 ++--- src/main.zig | 11 +++-- src/ppu.zig | 20 ++++----- src/scheduler.zig | 2 +- 12 files changed, 83 insertions(+), 105 deletions(-) diff --git a/src/Bus.zig b/src/Bus.zig index 5b8e912..a7cea1c 100644 --- a/src/Bus.zig +++ b/src/Bus.zig @@ -21,8 +21,6 @@ const log = std.log.scoped(.Bus); const rotr = @import("util.zig").rotr; const Self = @This(); -const panic_on_und_bus: bool = false; - pak: GamePak, bios: Bios, ppu: Ppu, @@ -73,7 +71,7 @@ pub fn handleDMATransfers(self: *Self) void { } } -fn isDmaRunning(self: *const Self) bool { +inline fn isDmaRunning(self: *const Self) bool { return self.dma._0.active or self.dma._1.active or self.dma._2.active or @@ -197,13 +195,4 @@ fn alignAddress(comptime T: type, address: u32) u32 { u8 => address, else => @compileError("Bus: Invalid read/write type"), }; -} - -fn undRead(comptime format: []const u8, args: anytype) u8 { - if (panic_on_und_bus) std.debug.panic(format, args) else log.warn(format, args); - return 0; -} - -fn undWrite(comptime format: []const u8, args: anytype) void { - if (panic_on_und_bus) std.debug.panic(format, args) else log.warn(format, args); -} +} \ No newline at end of file diff --git a/src/apu.zig b/src/apu.zig index 96ff52a..bb36b10 100644 --- a/src/apu.zig +++ b/src/apu.zig @@ -192,7 +192,7 @@ pub const Apu = struct { const right = (chA_right + chB_right + (psg_right * 0.05)) / 3; if (self.sampling_cycle != self.bias.sampling_cycle.read()) { - log.warn("Sampling Cycle changed from {} to {}", .{ self.sampling_cycle, self.bias.sampling_cycle.read() }); + log.info("Sampling Cycle changed from {} to {}", .{ self.sampling_cycle, self.bias.sampling_cycle.read() }); // Sample Rate Changed, Create a new Resampler since i can't figure out how to change // the parameters of the old one @@ -203,17 +203,17 @@ pub const Apu = struct { self.stream = SDL.SDL_NewAudioStream(SDL.AUDIO_F32, 2, @intCast(c_int, self.sampleRate()), SDL.AUDIO_F32, 2, host_sample_rate) orelse unreachable; } - while (SDL.SDL_AudioStreamAvailable(self.stream) > (@sizeOf(f32) * 2 * 0x800)) {} + // while (SDL.SDL_AudioStreamAvailable(self.stream) > (@sizeOf(f32) * 2 * 0x800)) {} _ = SDL.SDL_AudioStreamPut(self.stream, &[2]f32{ left, right }, 2 * @sizeOf(f32)); self.sched.push(.SampleAudio, self.sched.now() + self.sampleTicks() - late); } - inline fn sampleTicks(self: *const Self) u64 { + fn sampleTicks(self: *const Self) u64 { return (1 << 24) / self.sampleRate(); } - inline fn sampleRate(self: *const Self) u64 { + fn sampleRate(self: *const Self) u64 { return @as(u64, 1) << (15 + @as(u6, self.bias.sampling_cycle.read())); } @@ -1046,7 +1046,7 @@ const WaveDevice = struct { u8 => { self.buf[base + addr - 0x0400_0090] = value; }, - else => log.err("Unhandled {} write to Ch3 Wave RAM", .{T}), + else => @compileError("Ch3 WAVERAM: Unsupported write width"), } } }; diff --git a/src/bus/Bios.zig b/src/bus/Bios.zig index 1e7ab5d..38196d4 100644 --- a/src/bus/Bios.zig +++ b/src/bus/Bios.zig @@ -31,7 +31,7 @@ pub fn deinit(self: Self) void { pub fn read(self: *const Self, comptime T: type, addr: usize) T { if (self.buf) |buf| { if (addr > buf.len) { - log.err("Tried to read {} from {X:0>8} (open bus)", .{ T, addr }); + log.debug("Tried to read {} from {X:0>8} (open bus)", .{ T, addr }); return 0; } @@ -48,5 +48,5 @@ pub fn read(self: *const Self, comptime T: type, addr: usize) T { pub fn write(_: *Self, comptime T: type, addr: usize, value: T) void { @setCold(true); - log.err("Tried to write {} 0x{X:} to 0x{X:0>8} ", .{ T, value, addr }); + log.debug("Tried to write {} 0x{X:} to 0x{X:0>8} ", .{ T, value, addr }); } diff --git a/src/bus/backup.zig b/src/bus/backup.zig index c7b5bf4..c8dfe6b 100644 --- a/src/bus/backup.zig +++ b/src/bus/backup.zig @@ -86,7 +86,7 @@ pub const Backup = struct { return log.info("Loaded Save from {s}", .{file_path}); } - log.err("{s} is {} bytes, but we expected {} bytes", .{ file_path, file_buf.len, self.buf.len }); + log.debug("{s} is {} bytes, but we expected {} bytes", .{ file_path, file_buf.len, self.buf.len }); }, else => return SaveError.UnsupportedBackupKind, } diff --git a/src/bus/dma.zig b/src/bus/dma.zig index f4758a4..a891bd6 100644 --- a/src/bus/dma.zig +++ b/src/bus/dma.zig @@ -111,13 +111,6 @@ fn DmaController(comptime id: u2) type { self.writeCntHigh(@truncate(u16, word >> 16)); } - pub inline fn check(self: *Self, bus: *Bus) bool { - if (!self.active) return false; // FIXME: Check CNT register? - - self.step(bus); - return true; - } - pub fn step(self: *Self, bus: *Bus) bool { if (!self.active) return false; diff --git a/src/bus/io.zig b/src/bus/io.zig index b215e73..60095a5 100644 --- a/src/bus/io.zig +++ b/src/bus/io.zig @@ -179,11 +179,11 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void { 0x0400_010C => bus.tim._3.writeCnt(value), // Serial Communication 1 - 0x0400_0120 => log.warn("Wrote 0x{X:0>8} to SIODATA32", .{value}), + 0x0400_0120 => log.debug("Wrote 0x{X:0>8} to SIODATA32", .{value}), // Interrupts 0x0400_0200 => bus.io.setIrqs(value), - 0x0400_0204 => log.warn("Wrote 0x{X:0>8} to WAITCNT", .{value}), + 0x0400_0204 => log.debug("Wrote 0x{X:0>8} to WAITCNT", .{value}), 0x0400_0208 => bus.io.ime = value & 1 == 1, else => undWrite("Tried to write {} 0x{X:0>8} to 0x{X:0>8}", .{ T, value, address }), }, @@ -204,32 +204,32 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void { 0x0400_001A => bus.ppu.bg[2].vofs.raw = value, 0x0400_001C => bus.ppu.bg[3].hofs.raw = value, 0x0400_001E => bus.ppu.bg[3].vofs.raw = value, - 0x0400_0020 => log.warn("Wrote 0x{X:0>4} to BG2PA", .{value}), - 0x0400_0022 => log.warn("Wrote 0x{X:0>4} to BG2PB", .{value}), - 0x0400_0024 => log.warn("Wrote 0x{X:0>4} to BG2PC", .{value}), - 0x0400_0026 => log.warn("Wrote 0x{X:0>4} to BG2PD", .{value}), - 0x0400_0028 => log.warn("Wrote 0x{X:0>4} to BG2X_L", .{value}), - 0x0400_002A => log.warn("Wrote 0x{X:0>4} to BG2X_H", .{value}), - 0x0400_002C => log.warn("Wrote 0x{X:0>4} to BG2Y_L", .{value}), - 0x0400_002E => log.warn("Wrote 0x{X:0>4} to BG2Y_H", .{value}), - 0x0400_0030 => log.warn("Wrote 0x{X:0>4} to BG3PA", .{value}), - 0x0400_0032 => log.warn("Wrote 0x{X:0>4} to BG3PB", .{value}), - 0x0400_0034 => log.warn("Wrote 0x{X:0>4} to BG3PC", .{value}), - 0x0400_0036 => log.warn("Wrote 0x{X:0>4} to BG3PD", .{value}), - 0x0400_0038 => log.warn("Wrote 0x{X:0>4} to BG3X_L", .{value}), - 0x0400_003A => log.warn("Wrote 0x{X:0>4} to BG3X_H", .{value}), - 0x0400_003C => log.warn("Wrote 0x{X:0>4} to BG3Y_L", .{value}), - 0x0400_003E => log.warn("Wrote 0x{X:0>4} to BG3Y_H", .{value}), - 0x0400_0040 => log.warn("Wrote 0x{X:0>4} to WIN0H", .{value}), - 0x0400_0042 => log.warn("Wrote 0x{X:0>4} to WIN1H", .{value}), - 0x0400_0044 => log.warn("Wrote 0x{X:0>4} to WIN0V", .{value}), - 0x0400_0046 => log.warn("Wrote 0x{X:0>4} to WIN1V", .{value}), - 0x0400_0048 => log.warn("Wrote 0x{X:0>4} to WININ", .{value}), - 0x0400_004A => log.warn("Wrote 0x{X:0>4} to WINOUT", .{value}), - 0x0400_004C => log.warn("Wrote 0x{X:0>4} to MOSAIC", .{value}), - 0x0400_0050 => log.warn("Wrote 0x{X:0>4} to BLDCNT", .{value}), - 0x0400_0052 => log.warn("Wrote 0x{X:0>4} to BLDALPHA", .{value}), - 0x0400_0054 => log.warn("Wrote 0x{X:0>4} to BLDY", .{value}), + 0x0400_0020 => log.debug("Wrote 0x{X:0>4} to BG2PA", .{value}), + 0x0400_0022 => log.debug("Wrote 0x{X:0>4} to BG2PB", .{value}), + 0x0400_0024 => log.debug("Wrote 0x{X:0>4} to BG2PC", .{value}), + 0x0400_0026 => log.debug("Wrote 0x{X:0>4} to BG2PD", .{value}), + 0x0400_0028 => log.debug("Wrote 0x{X:0>4} to BG2X_L", .{value}), + 0x0400_002A => log.debug("Wrote 0x{X:0>4} to BG2X_H", .{value}), + 0x0400_002C => log.debug("Wrote 0x{X:0>4} to BG2Y_L", .{value}), + 0x0400_002E => log.debug("Wrote 0x{X:0>4} to BG2Y_H", .{value}), + 0x0400_0030 => log.debug("Wrote 0x{X:0>4} to BG3PA", .{value}), + 0x0400_0032 => log.debug("Wrote 0x{X:0>4} to BG3PB", .{value}), + 0x0400_0034 => log.debug("Wrote 0x{X:0>4} to BG3PC", .{value}), + 0x0400_0036 => log.debug("Wrote 0x{X:0>4} to BG3PD", .{value}), + 0x0400_0038 => log.debug("Wrote 0x{X:0>4} to BG3X_L", .{value}), + 0x0400_003A => log.debug("Wrote 0x{X:0>4} to BG3X_H", .{value}), + 0x0400_003C => log.debug("Wrote 0x{X:0>4} to BG3Y_L", .{value}), + 0x0400_003E => log.debug("Wrote 0x{X:0>4} to BG3Y_H", .{value}), + 0x0400_0040 => log.debug("Wrote 0x{X:0>4} to WIN0H", .{value}), + 0x0400_0042 => log.debug("Wrote 0x{X:0>4} to WIN1H", .{value}), + 0x0400_0044 => log.debug("Wrote 0x{X:0>4} to WIN0V", .{value}), + 0x0400_0046 => log.debug("Wrote 0x{X:0>4} to WIN1V", .{value}), + 0x0400_0048 => log.debug("Wrote 0x{X:0>4} to WININ", .{value}), + 0x0400_004A => log.debug("Wrote 0x{X:0>4} to WINOUT", .{value}), + 0x0400_004C => log.debug("Wrote 0x{X:0>4} to MOSAIC", .{value}), + 0x0400_0050 => log.debug("Wrote 0x{X:0>4} to BLDCNT", .{value}), + 0x0400_0052 => log.debug("Wrote 0x{X:0>4} to BLDALPHA", .{value}), + 0x0400_0054 => log.debug("Wrote 0x{X:0>4} to BLDY", .{value}), 0x0400_004E, 0x0400_0056 => {}, // Not used // Sound @@ -294,27 +294,27 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void { 0x0400_0110 => {}, // Not Used // Serial Communication 1 - 0x0400_0120 => log.warn("Wrote 0x{X:0>4} to SIOMULTI0", .{value}), - 0x0400_0122 => log.warn("Wrote 0x{X:0>4} to SIOMULTI1", .{value}), - 0x0400_0124 => log.warn("Wrote 0x{X:0>4} to SIOMULTI2", .{value}), - 0x0400_0126 => log.warn("Wrote 0x{X:0>4} to SIOMULTI3", .{value}), - 0x0400_0128 => log.warn("Wrote 0x{X:0>4} to SIOCNT", .{value}), - 0x0400_012A => log.warn("Wrote 0x{X:0>4} to SIOMLT_SEND", .{value}), + 0x0400_0120 => log.debug("Wrote 0x{X:0>4} to SIOMULTI0", .{value}), + 0x0400_0122 => log.debug("Wrote 0x{X:0>4} to SIOMULTI1", .{value}), + 0x0400_0124 => log.debug("Wrote 0x{X:0>4} to SIOMULTI2", .{value}), + 0x0400_0126 => log.debug("Wrote 0x{X:0>4} to SIOMULTI3", .{value}), + 0x0400_0128 => log.debug("Wrote 0x{X:0>4} to SIOCNT", .{value}), + 0x0400_012A => log.debug("Wrote 0x{X:0>4} to SIOMLT_SEND", .{value}), // Keypad Input - 0x0400_0130 => log.warn("Wrote 0x{X:0>4} to KEYINPUT. Ignored", .{value}), - 0x0400_0132 => log.warn("Wrote 0x{X:0>4} to KEYCNT", .{value}), + 0x0400_0130 => log.debug("Wrote 0x{X:0>4} to KEYINPUT. Ignored", .{value}), + 0x0400_0132 => log.debug("Wrote 0x{X:0>4} to KEYCNT", .{value}), // Serial Communication 2 - 0x0400_0134 => log.warn("Wrote 0x{X:0>4} to RCNT", .{value}), - 0x0400_0140 => log.warn("Wrote 0x{X:0>4} to JOYCNT", .{value}), - 0x0400_0158 => log.warn("Wrote 0x{X:0>4} to JOYSTAT", .{value}), + 0x0400_0134 => log.debug("Wrote 0x{X:0>4} to RCNT", .{value}), + 0x0400_0140 => log.debug("Wrote 0x{X:0>4} to JOYCNT", .{value}), + 0x0400_0158 => log.debug("Wrote 0x{X:0>4} to JOYSTAT", .{value}), 0x0400_0142, 0x0400_015A => {}, // Not Used // Interrupts 0x0400_0200 => bus.io.ie.raw = value, 0x0400_0202 => bus.io.irq.raw &= ~value, - 0x0400_0204 => log.warn("Wrote 0x{X:0>4} to WAITCNT", .{value}), + 0x0400_0204 => log.debug("Wrote 0x{X:0>4} to WAITCNT", .{value}), 0x0400_0208 => bus.io.ime = value & 1 == 1, 0x0400_0206, 0x0400_020A => {}, // Not Used else => undWrite("Tried to write {} 0x{X:0>4} to 0x{X:0>8}", .{ T, value, address }), @@ -354,10 +354,10 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void { 0x0400_0090...0x0400_009F => bus.apu.ch3.wave_dev.write(T, bus.apu.ch3.select, address, value), // Serial Communication 1 - 0x0400_0128 => log.warn("Wrote 0x{X:0>2} to SIOCNT (low)", .{value}), + 0x0400_0128 => log.debug("Wrote 0x{X:0>2} to SIOCNT (low)", .{value}), // Serial Communication 2 - 0x0400_0140 => log.warn("Wrote 0x{X:0>2} to JOYCNT (low)", .{value}), + 0x0400_0140 => log.debug("Wrote 0x{X:0>2} to JOYCNT (low)", .{value}), // Interrupts 0x0400_0208 => bus.io.ime = value & 1 == 1, diff --git a/src/cpu.zig b/src/cpu.zig index 06e8871..5ec9559 100644 --- a/src/cpu.zig +++ b/src/cpu.zig @@ -253,12 +253,12 @@ pub const Arm7tdmi = struct { pub fn step(self: *Self) void { if (self.cpsr.t.read()) { - const opcode = self.thumbFetch(); + const opcode = self.fetch(u16); if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode); thumb_lut[thumbIdx(opcode)](self, &self.bus, opcode); } else { - const opcode = self.fetch(); + const opcode = self.fetch(u32); if (enable_logging) if (self.log_file) |file| self.debug_log(file, opcode); if (checkCond(self.cpsr, @truncate(u4, opcode >> 28))) { @@ -272,12 +272,12 @@ pub const Arm7tdmi = struct { if (should_handle != 0) { self.bus.io.haltcnt = .Execute; - // log.info("An Interrupt was Fired!", .{}); + // log.debug("An Interrupt was Fired!", .{}); // Either IME is not true or I in CPSR is true // Don't handle interrupts if (!self.bus.io.ime or self.cpsr.i.read()) return; - // log.info("An interrupt was Handled!", .{}); + // log.debug("An interrupt was Handled!", .{}); // retAddr.gba says r15 on it's own is off by -04h in both ARM and THUMB mode const r15 = self.r[15] + 4; @@ -293,14 +293,11 @@ pub const Arm7tdmi = struct { } } - fn thumbFetch(self: *Self) u16 { - defer self.r[15] += 2; - return self.bus.read(u16, self.r[15]); - } + inline fn fetch(self: *Self, comptime T: type) T { + comptime std.debug.assert(T == u32 or T == u16); // Opcode may be 32-bit (ARM) or 16-bit (THUMB) + defer self.r[15] += if (T == u32) 4 else 2; - fn fetch(self: *Self) u32 { - defer self.r[15] += 4; - return self.bus.read(u32, self.r[15]); + return self.bus.read(T, self.r[15]); } pub fn fakePC(self: *const Self) u32 { diff --git a/src/cpu/arm/psr_transfer.zig b/src/cpu/arm/psr_transfer.zig index f9e3d17..0ac0595 100644 --- a/src/cpu/arm/psr_transfer.zig +++ b/src/cpu/arm/psr_transfer.zig @@ -17,7 +17,7 @@ pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrF // MRS const rd = opcode >> 12 & 0xF; - if (R and !cpu.hasSPSR()) log.warn("Tried to read SPSR from User/System Mode", .{}); + if (R and !cpu.hasSPSR()) log.err("Tried to read SPSR from User/System Mode", .{}); cpu.r[rd] = if (R) cpu.spsr.raw else cpu.cpsr.raw; }, 0b10 => { @@ -26,7 +26,7 @@ pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrF const rm_idx = opcode & 0xF; const right = if (I) rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) << 1) else cpu.r[rm_idx]; - if (R and !cpu.hasSPSR()) log.warn("Tried to write to SPSR in User/System Mode", .{}); + if (R and !cpu.hasSPSR()) log.err("Tried to write to SPSR in User/System Mode", .{}); if (R) { if (cpu.isPrivileged()) cpu.spsr.raw = fieldMask(&cpu.spsr, field_mask, right); diff --git a/src/emu.zig b/src/emu.zig index 2a37730..64f3dd0 100644 --- a/src/emu.zig +++ b/src/emu.zig @@ -57,12 +57,12 @@ pub fn runFrame(sched: *Scheduler, cpu: *Arm7tdmi) void { } pub fn runUnsync(quit: *Atomic(bool), sched: *Scheduler, cpu: *Arm7tdmi) void { - log.info("Unsynchronized EmuThread has begun", .{}); + log.info("Start unsynchronized emu thread", .{}); while (!quit.load(.Unordered)) runFrame(sched, cpu); } pub fn runSync(quit: *Atomic(bool), sched: *Scheduler, cpu: *Arm7tdmi) void { - log.info("Synchronized EmuThread has begun", .{}); + log.info("Start synchronized emu thread", .{}); var timer = Timer.start() catch unreachable; var wake_time: u64 = frame_period; @@ -79,7 +79,7 @@ pub fn runSync(quit: *Atomic(bool), sched: *Scheduler, cpu: *Arm7tdmi) void { } pub fn runUnsyncFps(quit: *Atomic(bool), fps: *FpsAverage, sched: *Scheduler, cpu: *Arm7tdmi) void { - log.info("Unsynchronized EmuThread with FPS Tracking has begun", .{}); + log.info("Start unsynchronized emu thread w/ fps tracking", .{}); var fps_timer = Timer.start() catch unreachable; while (!quit.load(.Unordered)) { @@ -89,7 +89,7 @@ pub fn runUnsyncFps(quit: *Atomic(bool), fps: *FpsAverage, sched: *Scheduler, cp } pub fn runSyncFps(quit: *Atomic(bool), fps: *FpsAverage, sched: *Scheduler, cpu: *Arm7tdmi) void { - log.info("Synchronized EmuThread has begun", .{}); + log.info("Start synchronized emu thread w/ fps tracking", .{}); var timer = Timer.start() catch unreachable; var fps_timer = Timer.start() catch unreachable; var wake_time: u64 = frame_period; @@ -110,7 +110,7 @@ pub fn runSyncFps(quit: *Atomic(bool), fps: *FpsAverage, sched: *Scheduler, cpu: } pub fn runBusyLoop(quit: *Atomic(bool), sched: *Scheduler, cpu: *Arm7tdmi) void { - log.info("Run EmuThread with spin-loop sync", .{}); + log.info("Start synchronized emu thread using busy loop", .{}); var timer = Timer.start() catch unreachable; var wake_time: u64 = frame_period; diff --git a/src/main.zig b/src/main.zig index 3cad404..f663e6a 100644 --- a/src/main.zig +++ b/src/main.zig @@ -65,9 +65,9 @@ pub fn main() anyerror!void { }; // Determine Save Directory - const save_path = try setupSavePath(alloc); - defer if (save_path) |path| alloc.free(path); - log.info("Save Path: {s}", .{save_path}); + const save_dir = try setupSavePath(alloc); + defer if (save_dir) |path| alloc.free(path); + log.info("Found save directory: {s}", .{save_dir}); // Initialize SDL _ = initSdl2(); @@ -77,7 +77,7 @@ pub fn main() anyerror!void { var scheduler = Scheduler.init(alloc); defer scheduler.deinit(); - const paths = .{ .bios = bios_path, .rom = rom_path, .save = save_path }; + const paths = .{ .bios = bios_path, .rom = rom_path, .save = save_dir }; var cpu = try Arm7tdmi.init(alloc, &scheduler, paths); defer cpu.deinit(); @@ -266,7 +266,6 @@ fn initAudio(apu: *Apu) SDL.SDL_AudioDeviceID { export fn audioCallback(userdata: ?*anyopaque, stream: [*c]u8, len: c_int) void { const apu = @ptrCast(*Apu, @alignCast(8, userdata)); - const result = SDL.SDL_AudioStreamGet(apu.stream, stream, len); + _ = SDL.SDL_AudioStreamGet(apu.stream, stream, len); - if (result < 0) log.err("Audio Callback Underflow", .{}); } diff --git a/src/ppu.zig b/src/ppu.zig index 54d1ab6..0f0b926 100644 --- a/src/ppu.zig +++ b/src/ppu.zig @@ -645,43 +645,43 @@ const Sprite = struct { }; } - inline fn x(self: *const Self) u9 { + fn x(self: *const Self) u9 { return self.attr1.x.read(); } - inline fn y(self: *const Self) u8 { + fn y(self: *const Self) u8 { return self.attr0.y.read(); } - inline fn is_8bpp(self: *const Self) bool { + fn is_8bpp(self: *const Self) bool { return self.attr0.is_8bpp.read(); } - inline fn shape(self: *const Self) u2 { + fn shape(self: *const Self) u2 { return self.attr0.shape.read(); } - inline fn size(self: *const Self) u2 { + fn size(self: *const Self) u2 { return self.attr1.size.read(); } - inline fn tile_id(self: *const Self) u10 { + fn tile_id(self: *const Self) u10 { return self.attr2.tile_id.read(); } - inline fn pal_bank(self: *const Self) u4 { + fn pal_bank(self: *const Self) u4 { return self.attr2.pal_bank.read(); } - inline fn h_flip(self: *const Self) bool { + fn h_flip(self: *const Self) bool { return self.attr1.h_flip.read(); } - inline fn v_flip(self: *const Self) bool { + fn v_flip(self: *const Self) bool { return self.attr1.v_flip.read(); } - inline fn priority(self: *const Self) u2 { + fn priority(self: *const Self) u2 { return self.attr2.rel_prio.read(); } }; diff --git a/src/scheduler.zig b/src/scheduler.zig index b1856d1..c3cb707 100644 --- a/src/scheduler.zig +++ b/src/scheduler.zig @@ -35,7 +35,7 @@ pub const Scheduler = struct { switch (event.kind) { .HeatDeath => { - log.err("A u64 overflowered. This *actually* should never happen.", .{}); + log.err("u64 overflow. This *actually* should never happen.", .{}); unreachable; }, .Draw => {