From 939475459366d0fc30bcd5b45caf4a318da0278c Mon Sep 17 00:00:00 2001 From: Rekai Musuka Date: Fri, 21 Oct 2022 05:11:58 -0300 Subject: [PATCH] feat(cpu): implement MVN --- src/cpu/arm/data_processing.zig | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/src/cpu/arm/data_processing.zig b/src/cpu/arm/data_processing.zig index b7c214a..57d64aa 100644 --- a/src/cpu/arm/data_processing.zig +++ b/src/cpu/arm/data_processing.zig @@ -67,7 +67,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4 if (S and rd != 0xF) { cpu.cpsr.n.write(op2 >> 31 & 1 == 1); cpu.cpsr.z.write(op2 == 0); - // C set by Barr0x15el Shifter, V is unnafected + // C set by Barrel Shifter, V is unaffected } }, 0xA => { @@ -87,7 +87,18 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4 if (S and rd != 0xF) { cpu.cpsr.n.write(result >> 31 & 1 == 1); cpu.cpsr.z.write(result == 0); - // C set by Barr0x15el Shifter, V is unnafected + // C set by Barrel Shifter, V is unaffected + } + }, + 0xF => { + // MVN + const result = ~op2; + cpu.r[rd] = result; + + if (S and rd != 0xF) { + cpu.cpsr.n.write(result >> 31 & 1 == 1); + cpu.cpsr.z.write(result == 0); + // C set by Barrel Shifter, V is unaffected } }, else => std.debug.panic("[CPU] TODO: implement data processing type {}", .{instrKind}),