From 9098a55ae36083e2206d1175c0406e4126f810fe Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Mon, 17 Jan 2022 11:35:41 -0400
Subject: [PATCH] feat(cpu): implement ARM SUB in data processing

---
 src/cpu/arm/data_processing.zig | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/cpu/arm/data_processing.zig b/src/cpu/arm/data_processing.zig
index 57d64aa..4f05ca1 100644
--- a/src/cpu/arm/data_processing.zig
+++ b/src/cpu/arm/data_processing.zig
@@ -29,6 +29,18 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4
             }
 
             switch (instrKind) {
+                0x2 => {
+                    // SUB
+                    const result = op1 -% op2;
+                    cpu.r[rd] = result;
+
+                    if (S and rd != 0xF) {
+                        cpu.cpsr.n.write(result >> 31 & 1 == 1);
+                        cpu.cpsr.z.write(result == 0);
+                        cpu.cpsr.c.write(op2 <= op1);
+                        cpu.cpsr.v.write(((op1 ^ result) & (~op2 ^ result)) >> 31 & 1 == 1);
+                    }
+                },
                 0x4 => {
                     // ADD
                     var result: u32 = undefined;