From 800ca798cd74131d3e27a8b1b884afb7a4cd1f0a Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Fri, 21 Oct 2022 05:12:05 -0300
Subject: [PATCH] feat(cpu): implement format19 THUMB instructions

---
 src/cpu.zig                |  7 +++++++
 src/cpu/thumb/format19.zig | 25 +++++++++++++++++++++++++
 2 files changed, 32 insertions(+)
 create mode 100644 src/cpu/thumb/format19.zig

diff --git a/src/cpu.zig b/src/cpu.zig
index 305a95b..210c468 100644
--- a/src/cpu.zig
+++ b/src/cpu.zig
@@ -26,6 +26,7 @@ const format5 = @import("cpu/thumb/format5.zig").format5;
 const format6 = @import("cpu/thumb/format6.zig").format6;
 const format12 = @import("cpu/thumb/format12.zig").format12;
 const format16 = @import("cpu/thumb/format16.zig").format16;
+const format19 = @import("cpu/thumb/format19.zig").format19;
 
 pub const ArmInstrFn = fn (*Arm7tdmi, *Bus, u32) void;
 pub const ThumbInstrFn = fn (*Arm7tdmi, *Bus, u16) void;
@@ -365,6 +366,12 @@ fn thumbPopulate() [0x400]ThumbInstrFn {
 
                 lut[i] = format16(cond);
             }
+
+            if (i >> 6 & 0xF == 0b1111) {
+                const is_low = i >> 5 & 1 == 1;
+
+                lut[i] = format19(is_low);
+            }
         }
 
         return lut;
diff --git a/src/cpu/thumb/format19.zig b/src/cpu/thumb/format19.zig
new file mode 100644
index 0000000..c2eab4d
--- /dev/null
+++ b/src/cpu/thumb/format19.zig
@@ -0,0 +1,25 @@
+const std = @import("std");
+
+const Bus = @import("../../Bus.zig");
+const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi;
+const InstrFn = @import("../../cpu.zig").ThumbInstrFn;
+const u32SignExtend = @import("../../util.zig").u32SignExtend;
+
+pub fn format19(comptime is_low: bool) InstrFn {
+    return struct {
+        fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void {
+            const offset = opcode & 0x3FF;
+
+            if (is_low) {
+                // Instruction 2
+                const old_pc = cpu.r[15];
+
+                cpu.r[15] = cpu.r[14] + (offset << 1);
+                cpu.r[14] = old_pc | 1;
+            } else {
+                // Instruction 1
+                cpu.r[14] = (cpu.fakePC() & 0xFFFF_FFFC) + (u32SignExtend(11, @as(u32, offset)) << 12);
+            }
+        }
+    }.inner;
+}