diff --git a/src/bus.zig b/src/bus.zig
index cc66138..03c12ab 100644
--- a/src/bus.zig
+++ b/src/bus.zig
@@ -32,7 +32,7 @@ pub const Bus = struct {
         }
 
         self.pak.writeHalfWord(addr, halfword);
-    } 
+    }
 
     pub fn readByte(self: *const @This(), addr: u32) u8 {
         return self.pak.readByte(addr);
diff --git a/src/cpu.zig b/src/cpu.zig
index 41df8f0..dbb758a 100644
--- a/src/cpu.zig
+++ b/src/cpu.zig
@@ -28,7 +28,7 @@ pub const ARM7TDMI = struct {
     pub inline fn step(self: *@This()) u64 {
         const opcode = self.fetch();
         // Debug
-        std.debug.print("R15: 0x{X:}\n", .{ opcode });
+        std.debug.print("R15: 0x{X:}\n", .{opcode});
 
         ARM_LUT[armIdx(opcode)](self, self.bus, opcode);
 
@@ -63,8 +63,8 @@ fn populate() [0x1000]InstrFn {
                 const instrKind = i >> 5 & 0x0F;
 
                 lut[i] = comptimeDataProcessing(I, S, instrKind);
-            } 
-            
+            }
+
             if (i >> 9 & 0x7 == 0b000 and i >> 6 & 0x01 == 0x00 and i & 0xF == 0x0) {
                 // Halfword and Signed Data Transfer with register offset
                 const P = i >> 8 & 0x01 == 0x01;
@@ -86,7 +86,7 @@ fn populate() [0x1000]InstrFn {
 
                 lut[i] = comptimeHalfSignedDataTransfer(P, U, I, W, L);
             }
-            
+
             if (i >> 10 & 0x3 == 0b01 and i & 0x01 == 0x00) {
                 const I = i >> 9 & 0x01 == 0x01;
                 const P = i >> 8 & 0x01 == 0x01;
@@ -97,11 +97,11 @@ fn populate() [0x1000]InstrFn {
 
                 lut[i] = comptimeSingleDataTransfer(I, P, U, B, W, L);
             }
-            
+
             if (i >> 9 & 0x7 == 0b101) {
                 const L = i >> 8 & 0x01 == 0x01;
                 lut[i] = comptimeBranch(L);
-            } 
+            }
         }
 
         return lut;
@@ -116,8 +116,8 @@ const CPSR = packed struct {
     _: u20,
     i: bool, // IRQ Disable
     f: bool, // FIQ Diable
-    t: bool, // State 
-    m: Mode, // Mode 
+    t: bool, // State
+    m: Mode, // Mode
 };
 
 const Mode = enum(u5) {
@@ -130,9 +130,6 @@ const Mode = enum(u5) {
     System = 0b11111,
 };
 
-
-
-
 fn undefined_instr(_: *ARM7TDMI, _: *Bus, opcode: u32) void {
     const id = armIdx(opcode);
     std.debug.panic("[0x{X:}] 0x{X:} is an illegal opcode", .{ id, opcode });
diff --git a/src/cpu/half_signed_data_transfer.zig b/src/cpu/half_signed_data_transfer.zig
index 20735d2..d567bb4 100644
--- a/src/cpu/half_signed_data_transfer.zig
+++ b/src/cpu/half_signed_data_transfer.zig
@@ -27,9 +27,9 @@ pub fn comptimeHalfSignedDataTransfer(comptime P: bool, comptime U: bool, compti
             var address = if (P) modified_base else base;
 
             if (L) {
-                switch(@truncate(u2, opcode >> 5)) {
+                switch (@truncate(u2, opcode >> 5)) {
                     0b00 => {
-                        // SWP 
+                        // SWP
                         std.debug.panic("TODO: Implement SWP", .{});
                     },
                     0b01 => {
@@ -46,7 +46,7 @@ pub fn comptimeHalfSignedDataTransfer(comptime P: bool, comptime U: bool, compti
                         // LDRSH
                         const halfword = bus.readHalfWord(address);
                         cpu.r[rd] = util.u32_sign_extend(@as(u32, halfword), 16);
-                    }
+                    },
                 }
             } else {
                 if (opcode >> 5 & 0x01 == 0x01) {
@@ -64,4 +64,4 @@ pub fn comptimeHalfSignedDataTransfer(comptime P: bool, comptime U: bool, compti
             if (W and P) cpu.r[rn] = address;
         }
     }.halfSignedDataTransfer;
-}
\ No newline at end of file
+}
diff --git a/src/util.zig b/src/util.zig
index e621652..88a19c1 100644
--- a/src/util.zig
+++ b/src/util.zig
@@ -1,6 +1,5 @@
 const std = @import("std");
 
-
 pub fn u32_sign_extend(value: u32, bitSize: anytype) u32 {
     const amount: u5 = 32 - bitSize;
     return @bitCast(u32, @bitCast(i32, value << amount) >> amount);