From 75921d64136d4daa7a691f11b8547cb0196efe4d Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Fri, 21 Oct 2022 05:12:16 -0300
Subject: [PATCH] fix: PC is 12 ahead when it is rd in str and strb

---
 src/cpu/arm/single_data_transfer.zig | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/cpu/arm/single_data_transfer.zig b/src/cpu/arm/single_data_transfer.zig
index 39f166b..103bde0 100644
--- a/src/cpu/arm/single_data_transfer.zig
+++ b/src/cpu/arm/single_data_transfer.zig
@@ -38,11 +38,12 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
             } else {
                 if (B) {
                     // STRB
-                    bus.write8(address, @truncate(u8, cpu.r[rd]));
+                    const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
+                    bus.write8(address, @truncate(u8, value));
                 } else {
                     // STR
-                    const force_aligned = address & 0xFFFF_FFFC;
-                    bus.write32(force_aligned, cpu.r[rd]);
+                    const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
+                    bus.write32(address & 0xFFFF_FFFC, value);
                 }
             }