From 6e66298def8d965915dc989cda3689995c0be398 Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Sat, 2 Jul 2022 03:42:27 -0300
Subject: [PATCH] fix: flush pipline on mode change

---
 src/cpu.zig | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/cpu.zig b/src/cpu.zig
index 5536f87..09cb80b 100644
--- a/src/cpu.zig
+++ b/src/cpu.zig
@@ -156,6 +156,14 @@ pub const Arm7tdmi = struct {
 
     pub fn setCpsr(self: *Self, value: u32) void {
         if (value & 0x1F != self.cpsr.raw & 0x1F) self.changeModeFromIdx(@truncate(u5, value & 0x1F));
+
+        const new: PSR = .{ .raw = value };
+        if (self.cpsr.t.read() != new.t.read()) {
+            // If THUMB to ARM or ARM to THUMB, flush pipeline
+            self.r[15] &= if (new.t.read()) ~@as(u32, 1) else ~@as(u32, 3);
+            self.pipe.flush();
+        }
+
         self.cpsr.raw = value;
     }
 
@@ -239,9 +247,6 @@ pub const Arm7tdmi = struct {
                 self.spsr = self.banked_spsr[bankedSpsrIndex(next)];
             },
         }
-
-        self.cpsr.mode.write(@enumToInt(next));
-        self.pipe.flush();
     }
 
     pub fn fastBoot(self: *Self) void {