From 6da9e965bb7ce1c154c5b343aacb2c14a5470fde Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Wed, 13 Jul 2022 02:08:31 -0300
Subject: [PATCH] chore: misc pipeline fixes

---
 src/cpu.zig                               |  8 ++------
 src/cpu/arm/block_data_transfer.zig       |  8 +++++---
 src/cpu/arm/half_signed_data_transfer.zig | 16 ++--------------
 src/cpu/arm/single_data_transfer.zig      |  8 ++++----
 4 files changed, 13 insertions(+), 27 deletions(-)

diff --git a/src/cpu.zig b/src/cpu.zig
index bb0c64a..18a0c63 100644
--- a/src/cpu.zig
+++ b/src/cpu.zig
@@ -329,8 +329,8 @@ pub const Arm7tdmi = struct {
             if (!self.bus.io.ime or self.cpsr.i.read()) return;
             // log.debug("An interrupt was Handled!", .{});
 
-            // retAddr.gba says r15 on it's own is off by -04h in both ARM and THUMB mode
-            const r15 = self.r[15] + 4;
+            // FIXME: Is the return address ahead?
+            const r15 = self.r[15];
             const cpsr = self.cpsr.raw;
 
             self.changeMode(.Irq);
@@ -354,10 +354,6 @@ pub const Arm7tdmi = struct {
         return self.bus.read(T, self.r[15]);
     }
 
-    pub fn fakePC(self: *const Self) u32 {
-        return self.r[15] + 4;
-    }
-
     fn debug_log(self: *const Self, file: *const File, opcode: u32) void {
         if (self.binary_log) {
             self.skyLog(file) catch unreachable;
diff --git a/src/cpu/arm/block_data_transfer.zig b/src/cpu/arm/block_data_transfer.zig
index 09e74c7..123913f 100644
--- a/src/cpu/arm/block_data_transfer.zig
+++ b/src/cpu/arm/block_data_transfer.zig
@@ -55,8 +55,10 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
 
                 if (L) {
                     cpu.r[15] = bus.read(u32, und_addr);
+                    cpu.pipe.flush();
                 } else {
-                    bus.write(u32, und_addr, cpu.r[15] + 8);
+                    // FIXME: Should r15 on write be +12 ahead?
+                    bus.write(u32, und_addr, cpu.r[15] + 4);
                 }
 
                 cpu.r[rn] = if (U) cpu.r[rn] + 0x40 else cpu.r[rn] - 0x40;
@@ -100,9 +102,9 @@ pub fn blockDataTransfer(comptime P: bool, comptime U: bool, comptime S: bool, c
                     // Always Transfer User mode Registers
                     // This happens regardless if r15 is in the list
                     const value = cpu.getUserModeRegister(i);
-                    bus.write(u32, address, value + if (i == 0xF) 8 else @as(u32, 0)); // PC is already 4 ahead to make 12
+                    bus.write(u32, address, value + if (i == 0xF) 4 else @as(u32, 0)); // PC is already 8 ahead to make 12
                 } else {
-                    bus.write(u32, address, cpu.r[i] + if (i == 0xF) 8 else @as(u32, 0));
+                    bus.write(u32, address, cpu.r[i] + if (i == 0xF) 4 else @as(u32, 0));
                 }
             }
         }
diff --git a/src/cpu/arm/half_signed_data_transfer.zig b/src/cpu/arm/half_signed_data_transfer.zig
index 5ffae2c..ae9b1cb 100644
--- a/src/cpu/arm/half_signed_data_transfer.zig
+++ b/src/cpu/arm/half_signed_data_transfer.zig
@@ -15,20 +15,8 @@ pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I:
             const rm = opcode & 0xF;
             const imm_offset_high = opcode >> 8 & 0xF;
 
-            var base: u32 = undefined;
-            if (rn == 0xF) {
-                base = cpu.fakePC();
-                if (!L) base += 4;
-            } else {
-                base = cpu.r[rn];
-            }
-
-            var offset: u32 = undefined;
-            if (I) {
-                offset = imm_offset_high << 4 | rm;
-            } else {
-                offset = cpu.r[rm];
-            }
+            const base = cpu.r[rn] + if (!L) 4 else @as(u32, 0);
+            const offset = if (I) imm_offset_high << 4 | rm else cpu.r[rm];
 
             const modified_base = if (U) base +% offset else base -% offset;
             var address = if (P) modified_base else base;
diff --git a/src/cpu/arm/single_data_transfer.zig b/src/cpu/arm/single_data_transfer.zig
index c3a1555..d3ca113 100644
--- a/src/cpu/arm/single_data_transfer.zig
+++ b/src/cpu/arm/single_data_transfer.zig
@@ -14,8 +14,8 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
             const rn = opcode >> 16 & 0xF;
             const rd = opcode >> 12 & 0xF;
 
-            // If L is set, there is an offset of 12 from the instruction to the PC
-            const base = cpu.r[rn] + if (!L) 4 else @as(u32, 0);
+            // rn is r15 and L is not set, the PC is 12 ahead
+            const base = cpu.r[rn] + if (!L and rn == 0xF) 4 else @as(u32, 0);
 
             const offset = if (I) shifter.immShift(false, cpu, opcode) else opcode & 0xFFF;
 
@@ -35,11 +35,11 @@ pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool,
             } else {
                 if (B) {
                     // STRB
-                    const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
+                    const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0); // PC is 12 ahead
                     bus.write(u8, address, @truncate(u8, value));
                 } else {
                     // STR
-                    const value = if (rd == 0xF) cpu.r[rd] + 8 else cpu.r[rd];
+                    const value = cpu.r[rd] + if (rd == 0xF) 4 else @as(u32, 0);
                     bus.write(u32, address, value);
                 }
             }