From 67f7c492701a45638676029e05ec0082b3d28c44 Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Fri, 26 Aug 2022 23:59:59 -0500
Subject: [PATCH] fix: advance r15, even when the pipeline is reloaded from the
 scheduler

The PC would fall behind whenever an IRQ was called because the pipeline
was reloaded (+8 to PC), however that was never actually done by any code

Now, the PC is always incremented when the pipeline is reloaded
---
 src/core/cpu.zig | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/core/cpu.zig b/src/core/cpu.zig
index 541a88a..62c0137 100644
--- a/src/core/cpu.zig
+++ b/src/core/cpu.zig
@@ -456,8 +456,7 @@ pub const Arm7tdmi = struct {
             }
         }
 
-        if (self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
-        self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
+        if (!self.pipe.flushed) self.r[15] += if (self.cpsr.t.read()) 2 else @as(u32, 4);
         self.pipe.flushed = false;
     }
 
@@ -704,6 +703,8 @@ const Pipline = struct {
 
         self.stage[0] = cpu.bus.read(T, cpu.r[15]);
         self.stage[1] = cpu.bus.read(T, cpu.r[15] + if (T == u32) 4 else @as(u32, 2));
+
+        cpu.r[15] += if (T == u32) 8 else @as(u32, 4);
         self.flushed = true;
     }
 };