From 603e4b6fdff5e8a0a8fd88c7368fd4e18a3d134b Mon Sep 17 00:00:00 2001 From: Rekai Musuka Date: Fri, 21 Oct 2022 05:12:18 -0300 Subject: [PATCH] chore: make use of scoped logging --- src/Bus.zig | 13 +++++++------ src/cpu/arm/psr_transfer.zig | 6 ++++-- src/cpu/thumb/data_processing.zig | 9 ++++++++- src/scheduler.zig | 3 ++- 4 files changed, 21 insertions(+), 10 deletions(-) diff --git a/src/Bus.zig b/src/Bus.zig index 420658b..07524ad 100644 --- a/src/Bus.zig +++ b/src/Bus.zig @@ -9,6 +9,7 @@ const Ppu = @import("ppu.zig").Ppu; const Scheduler = @import("scheduler.zig").Scheduler; const Allocator = std.mem.Allocator; +const log = std.log.scoped(.Bus); const Self = @This(); pak: GamePak, @@ -56,7 +57,7 @@ pub fn read32(self: *const Self, addr: u32) u32 { 0x0C00_0000...0x0DFF_FFFF => self.pak.get32(addr - 0x0C00_0000), else => { - std.log.warn("[Bus:32] ZBA tried to read from 0x{X:}", .{addr}); + log.warn("32-bit read from 0x{X:0>8}", .{addr}); return 0x0000_0000; }, }; @@ -76,7 +77,7 @@ pub fn write32(self: *Self, addr: u32, word: u32) void { 0x0600_0000...0x0601_7FFF => self.ppu.vram.set32(addr - 0x0600_0000, word), 0x0700_0000...0x0700_03FF => std.debug.panic("[Bus:32] wrote 0x{X:} to 0x{X:} in OAM", .{ word, addr }), - else => std.log.warn("[Bus:32] ZBA tried to write 0x{X:} to 0x{X:}", .{ word, addr }), + else => log.warn("32-bit write of 0x{X:0>8} to 0x{X:0>8}", .{ word, addr }), } } @@ -99,7 +100,7 @@ pub fn read16(self: *const Self, addr: u32) u16 { 0x0C00_0000...0x0DFF_FFFF => self.pak.get16(addr - 0x0C00_0000), else => { - std.log.warn("[Bus:16] ZBA tried to read from 0x{X:}", .{addr}); + log.warn("16-bit read from 0x{X:0>8}", .{addr}); return 0x0000; }, }; @@ -118,7 +119,7 @@ pub fn write16(self: *Self, addr: u32, halfword: u16) void { 0x0600_0000...0x0601_7FFF => self.ppu.vram.set16(addr - 0x0600_0000, halfword), 0x0700_0000...0x0700_03FF => std.debug.panic("[Bus:16] write 0x{X:} to 0x{X:} in OAM", .{ halfword, addr }), - else => std.log.warn("[Bus:16] ZBA tried to write 0x{X:} to 0x{X:}", .{ halfword, addr }), + else => log.warn("16-bit write of 0x{X:0>4} to 0x{X:0>8}", .{ halfword, addr }), } } @@ -142,7 +143,7 @@ pub fn read8(self: *const Self, addr: u32) u8 { 0x0E00_0000...0x0E00_FFFF => std.debug.panic("[Bus:8] read from 0x{X:} in Game Pak SRAM", .{addr}), else => { - std.log.warn("[Bus:8] ZBA tried to read from 0x{X:}", .{addr}); + log.warn("8-bit read from 0x{X:0>8}", .{addr}); return 0x00; }, }; @@ -157,6 +158,6 @@ pub fn write8(self: *Self, addr: u32, byte: u8) void { // External Memory (Game Pak) 0x0E00_0000...0x0E00_FFFF => std.debug.panic("[Bus:8] write 0x{X:} to 0x{X:} in Game Pak SRAM", .{ byte, addr }), - else => std.log.warn("[Bus:8] ZBA tried to write 0x{X:} to 0x{X:}", .{ byte, addr }), + else => log.warn("8-bit write of 0x{X:0>2} to 0x{X:0>8}", .{ byte, addr }), } } diff --git a/src/cpu/arm/psr_transfer.zig b/src/cpu/arm/psr_transfer.zig index f3abf07..8eb3e94 100644 --- a/src/cpu/arm/psr_transfer.zig +++ b/src/cpu/arm/psr_transfer.zig @@ -5,6 +5,8 @@ const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const InstrFn = @import("../../cpu.zig").ArmInstrFn; const PSR = @import("../../cpu.zig").PSR; +const log = std.log.scoped(.PsrTransfer); + pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrFn { return struct { fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void { @@ -13,7 +15,7 @@ pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrF // MRS const rd = opcode >> 12 & 0xF; - if (R and !cpu.hasSPSR()) std.log.warn("[CPU/PSR Transfer] Tried to read SPSR from User/System Mode", .{}); + if (R and !cpu.hasSPSR()) log.warn("Tried to read SPSR from User/System Mode", .{}); cpu.r[rd] = if (R) cpu.spsr.raw else cpu.cpsr.raw; }, 0b10 => { @@ -22,7 +24,7 @@ pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrF const rm_idx = opcode & 0xF; const right = if (I) std.math.rotr(u32, opcode & 0xFF, (opcode >> 8 & 0xF) << 1) else cpu.r[rm_idx]; - if (R and !cpu.hasSPSR()) std.log.warn("[CPU/PSR Transfer] Tried to write to SPSR User/System Mode", .{}); + if (R and !cpu.hasSPSR()) log.warn("Tried to write to SPSR in User/System Mode", .{}); if (R) { if (cpu.isPrivileged()) cpu.spsr.raw = fieldMask(&cpu.spsr, field_mask, right); diff --git a/src/cpu/thumb/data_processing.zig b/src/cpu/thumb/data_processing.zig index 2cb53e3..ba46ba1 100644 --- a/src/cpu/thumb/data_processing.zig +++ b/src/cpu/thumb/data_processing.zig @@ -1,3 +1,5 @@ +const std = @import("std"); + const Bus = @import("../../Bus.zig"); const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const InstrFn = @import("../../cpu.zig").ThumbInstrFn; @@ -8,6 +10,8 @@ const sub = @import("../arm/data_processing.zig").sub; const cmp = @import("../arm/data_processing.zig").cmp; const setLogicOpFlags = @import("../arm/data_processing.zig").setLogicOpFlags; +const log = std.log.scoped(.Thumb1); + pub fn format1(comptime op: u2, comptime offset: u5) InstrFn { return struct { fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u16) void { @@ -41,7 +45,10 @@ pub fn format1(comptime op: u2, comptime offset: u5) InstrFn { break :blk shifter.arithmeticRight(true, &cpu.cpsr, cpu.r[rs], offset); } }, - else => cpu.panic("[CPU|THUMB|Fmt1] {} is an invalid op", .{op}), + else => { + log.err("0b{b:0>2} is not a valid op", .{op}); + // TODO: Should we panic here? + }, }; // Equivalent to an ARM MOVS diff --git a/src/scheduler.zig b/src/scheduler.zig index afbd933..7048e4d 100644 --- a/src/scheduler.zig +++ b/src/scheduler.zig @@ -6,6 +6,7 @@ const Arm7tdmi = @import("cpu.zig").Arm7tdmi; const Order = std.math.Order; const PriorityQueue = std.PriorityQueue; const Allocator = std.mem.Allocator; +const log = std.log.scoped(.Scheduler); pub const Scheduler = struct { const Self = @This(); @@ -29,7 +30,7 @@ pub const Scheduler = struct { if (should_handle) { const event = self.queue.remove(); - // std.log.info("[Scheduler] Handle {} at {} ticks", .{ event.kind, self.tick }); + // log.debug("Handle {} @ tick = {}", .{ event.kind, self.tick }); switch (event.kind) { .HeatDeath => {