From 5d0bc1b335a0d4039ca8583054ca6a80290e604f Mon Sep 17 00:00:00 2001 From: Rekai Musuka Date: Fri, 21 Oct 2022 05:11:59 -0300 Subject: [PATCH] chore(cpu): refactor the barrel shifter once again --- src/cpu/arm/barrel_shifter.zig | 157 +++++++++++++++++++++----------- src/cpu/arm/data_processing.zig | 19 ++-- 2 files changed, 110 insertions(+), 66 deletions(-) diff --git a/src/cpu/arm/barrel_shifter.zig b/src/cpu/arm/barrel_shifter.zig index b1827f1..d8f5717 100644 --- a/src/cpu/arm/barrel_shifter.zig +++ b/src/cpu/arm/barrel_shifter.zig @@ -3,82 +3,142 @@ const std = @import("std"); const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const CPSR = @import("../../cpu.zig").PSR; -pub fn exec(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 { - var shift_amt: u8 = undefined; +pub fn execute(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 { + var result: u32 = undefined; if (opcode >> 4 & 1 == 1) { - shift_amt = @truncate(u8, cpu.r[opcode >> 8 & 0xF]); + result = registerShift(S, cpu, opcode); } else { - shift_amt = @truncate(u8, opcode >> 7 & 0x1F); + result = immShift(S, cpu, opcode); } - const rm = cpu.r[opcode & 0xF]; - var value: u32 = undefined; - if (rm == 0xF) { - value = cpu.fakePC() + 4; // 12 ahead - } else { - value = cpu.r[opcode & 0xF]; - } + return result; +} + +fn registerShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 { + const rs_idx = opcode >> 8 & 0xF; + const rs = @truncate(u8, cpu.r[rs_idx]); + + const rm_idx = opcode & 0xF; + const rm = if (rm_idx == 0xF) cpu.fakePC() + 4 else cpu.r[rm_idx]; return switch (@truncate(u2, opcode >> 5)) { - 0b00 => logicalLeft(S, &cpu.cpsr, value, shift_amt), - 0b01 => logicalRight(S, &cpu.cpsr, value, shift_amt), - 0b10 => arithmeticRight(S, &cpu.cpsr, value, shift_amt), - 0b11 => rotateRight(S, &cpu.cpsr, value, shift_amt), + 0b00 => logicalLeft(S, &cpu.cpsr, rm, rs), + 0b01 => logicalRight(S, &cpu.cpsr, rm, rs), + 0b10 => arithmeticRight(S, &cpu.cpsr, rm, rs), + 0b11 => rotateRight(S, &cpu.cpsr, rm, rs), }; } -pub fn logicalLeft(comptime S: bool, cpsr: *CPSR, rm: u32, amount: u8) u32 { - const shift_amt = @truncate(u5, amount); +fn immShift(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 { + const amount = @truncate(u8, opcode >> 7 & 0x1F); + + const rm_idx = opcode & 0xF; + const rm = if (rm_idx == 0xF) cpu.fakePC() + 4 else cpu.r[rm_idx]; + + var result: u32 = undefined; + if (amount == 0) { + switch (@truncate(u2, opcode >> 5)) { + 0b00 => { + // LSL #0 + result = rm; + }, + 0b01 => { + // LSR #0 aka LSR #32 + if (S) cpu.cpsr.c.write(rm >> 31 & 1 == 1); + result = 0x0000_0000; + }, + 0b10 => { + // ASR #0 aka ASR #32 + result = @bitCast(u32, @bitCast(i32, rm) >> 31); + if (S) cpu.cpsr.c.write(result >> 31 & 1 == 1); + }, + 0b11 => { + // ROR #0 aka RRX + const carry: u32 = @boolToInt(cpu.cpsr.c.read()); + if (S) cpu.cpsr.c.write(rm & 1 == 1); + + result = (carry << 31) | (rm >> 1); + }, + } + } else { + switch (@truncate(u2, opcode >> 5)) { + 0b00 => result = logicalLeft(S, &cpu.cpsr, rm, amount), + 0b01 => result = logicalRight(S, &cpu.cpsr, rm, amount), + 0b10 => result = arithmeticRight(S, &cpu.cpsr, rm, amount), + 0b11 => result = rotateRight(S, &cpu.cpsr, rm, amount), + } + } + + return result; +} + +pub fn logicalLeft(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 { + const amount = @truncate(u5, total_amount); const bit_count: u8 = @typeInfo(u32).Int.bits; var result: u32 = 0x0000_0000; - - if (amount < bit_count) { + if (total_amount < bit_count) { // We can perform a well-defined shift here + result = rm << amount; - // FIXME: We assume cpu.r[rs] == 0 and imm_shift == 0 are equivalent - if (S and shift_amt != 0) { - const carry_bit = @truncate(u5, bit_count - shift_amt); + if (S) { + const carry_bit = @truncate(u5, bit_count - amount); cpsr.c.write(rm >> carry_bit & 1 == 1); } - - result = rm << shift_amt; - } else if (amount == bit_count) { - // Shifted all bits out, carry bit is bit 0 of rm - if (S) cpsr.c.write(rm & 1 == 1); } else { - // Shifted all bits out, carry bit has also been shifted out - if (S) cpsr.c.write(false); + if (S) { + if (total_amount == bit_count) { + // Shifted all bits out, carry bit is bit 0 of rm + cpsr.c.write(rm & 1 == 1); + } else { + cpsr.c.write(false); + } + } } return result; } -pub fn logicalRight(comptime S: bool, cpsr: *CPSR, rm: u32, amount: u32) u32 { - const shift_amt = @truncate(u5, amount); +pub fn logicalRight(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u32) u32 { + const amount = @truncate(u5, total_amount); const bit_count: u8 = @typeInfo(u32).Int.bits; var result: u32 = 0x0000_0000; - - if (amount == 0 or amount == bit_count) { - // Actualy LSR #32 - if (S) cpsr.c.write(rm >> 31 & 1 == 1); - } else if (amount < bit_count) { + if (total_amount < bit_count) { // We can perform a well-defined shift - const carry_bit = shift_amt - 1; - if (S) cpsr.c.write(rm >> carry_bit & 1 == 1); - - result = rm >> shift_amt; + result = rm >> amount; + if (S) cpsr.c.write(rm >> (amount - 1) & 1 == 1); } else { - // All bits have been shifted out, including carry bit - if (S) cpsr.c.write(false); + if (S) { + if (total_amount == bit_count) { + // LSR #32 + cpsr.c.write(rm >> 31 & 1 == 1); + } else { + // All bits have been shifted out, including carry bit + cpsr.c.write(false); + } + } } return result; } -pub fn arithmeticRight(comptime _: bool, _: *CPSR, _: u32, _: u8) u32 { - // @bitCast(u32, @bitCast(i32, r_val) >> @truncate(u5, amount)) +pub fn arithmeticRight(comptime S: bool, cpsr: *CPSR, rm: u32, total_amount: u8) u32 { + const amount = @truncate(u5, total_amount); + const bit_count: u8 = @typeInfo(u32).Int.bits; + + var result: u32 = 0x0000_0000; + if (total_amount < bit_count) { + result = @bitCast(u32, @bitCast(i32, rm) >> amount); + if (S) cpsr.c.write(rm >> (amount - 1) & 1 == 1); + } else { + if (S) { + // ASR #32 and ASR #>32 have the same result + result = @bitCast(u32, @bitCast(i32, rm) >> 31); + cpsr.c.write(result >> 31 & 1 == 1); + } + } + std.debug.panic("[BarrelShifter] implement arithmetic shift right", .{}); } @@ -91,12 +151,3 @@ pub fn rotateRight(comptime S: bool, cpsr: *CPSR, rm: u32, amount: u8) u32 { return result; } - -pub fn rotateRightExtended(comptime S: bool, cpsr: *CPSR, rm: u32) u32 { - if (!S) std.debug.panic("[BarrelShifter] Turns out I don't know how RRX works", .{}); - - const carry: u32 = @boolToInt(cpsr.c.read()); - cpsr.c.write(rm & 1 == 1); - - return (carry << 31) | (rm >> 1); -} diff --git a/src/cpu/arm/data_processing.zig b/src/cpu/arm/data_processing.zig index f648d56..b24bfd2 100644 --- a/src/cpu/arm/data_processing.zig +++ b/src/cpu/arm/data_processing.zig @@ -1,6 +1,6 @@ const std = @import("std"); -const BarrelShifter = @import("barrel_shifter.zig"); +const shifter = @import("barrel_shifter.zig"); const Bus = @import("../../Bus.zig"); const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const InstrFn = @import("../../cpu.zig").ArmInstrFn; @@ -11,21 +11,14 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4 const rd = opcode >> 12 & 0xF; const rn = opcode >> 16 & 0xF; - if (S and rd == 0xF) std.debug.panic("[CPU] Data Processing Instruction w/ S set and Rd == 15", .{}); - - var op1: u32 = undefined; - if (rn == 0xF) { - op1 = cpu.fakePC(); - } else { - op1 = cpu.r[rn]; - } + const op1 = if (rn == 0xF) cpu.fakePC() else cpu.r[rn]; var op2: u32 = undefined; if (I) { const amount = @truncate(u8, (opcode >> 8 & 0xF) << 1); - op2 = BarrelShifter.rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount); + op2 = shifter.rotateRight(S, &cpu.cpsr, opcode & 0xFF, amount); } else { - op2 = BarrelShifter.exec(S, cpu, opcode); + op2 = shifter.execute(S, cpu, opcode); } switch (instrKind) { @@ -77,7 +70,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4 cpu.cpsr.n.write(result >> 31 & 1 == 1); cpu.cpsr.z.write(result == 0); // Barrel Shifter should always calc CPSR C in TST - if (!S) _ = BarrelShifter.exec(true, cpu, opcode); + if (!S) _ = shifter.execute(true, cpu, opcode); }, 0x9 => { // TEQ @@ -86,7 +79,7 @@ pub fn dataProcessing(comptime I: bool, comptime S: bool, comptime instrKind: u4 cpu.cpsr.n.write(result >> 31 & 1 == 1); cpu.cpsr.z.write(result == 0); // Barrel Shifter should always calc CPSR C in TEQ - if (!S) _ = BarrelShifter.exec(true, cpu, opcode); + if (!S) _ = shifter.execute(true, cpu, opcode); }, 0xD => { // MOV