From 523b9d2736ede5c948e591021361713fb0042a1a Mon Sep 17 00:00:00 2001 From: Rekai Musuka Date: Fri, 21 Oct 2022 05:12:12 -0300 Subject: [PATCH] feat(cpu): implement THUMB format11 --- src/cpu.zig | 7 +++++-- src/cpu/thumb/format11.zig | 21 +++++++++++++++++++++ 2 files changed, 26 insertions(+), 2 deletions(-) create mode 100644 src/cpu/thumb/format11.zig diff --git a/src/cpu.zig b/src/cpu.zig index c8de217..485452e 100644 --- a/src/cpu.zig +++ b/src/cpu.zig @@ -31,6 +31,7 @@ const format6 = @import("cpu/thumb/format6.zig").format6; const format78 = @import("cpu/thumb/format78.zig").format78; const format9 = @import("cpu/thumb/format9.zig").format9; const format10 = @import("cpu/thumb/format10.zig").format10; +const format11 = @import("cpu/thumb/format11.zig").format11; const format12 = @import("cpu/thumb/format12.zig").format12; const format13 = @import("cpu/thumb/format13.zig").format13; const format14 = @import("cpu/thumb/format14.zig").format14; @@ -486,8 +487,10 @@ fn thumbPopulate() [0x400]ThumbInstrFn { lut[i] = format10(L, offset); } else if (i >> 6 & 0xF == 0b1001) { - // Format 11 | SP-relative load / store - lut[i] = thumbUndefined; + const L = i >> 5 & 1 == 1; + const rd = i >> 2 & 0x3; + + lut[i] = format11(L, rd); } else if (i >> 6 & 0xF == 0b1010) { const isSP = i >> 5 & 1 == 1; const rd = i >> 2 & 0x7; diff --git a/src/cpu/thumb/format11.zig b/src/cpu/thumb/format11.zig new file mode 100644 index 0000000..b17783d --- /dev/null +++ b/src/cpu/thumb/format11.zig @@ -0,0 +1,21 @@ +const std = @import("std"); + +const Bus = @import("../../Bus.zig"); +const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; +const InstrFn = @import("../../cpu.zig").ThumbInstrFn; + +pub fn format11(comptime L: bool, comptime rd: u3) InstrFn { + return struct { + fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void { + const offset = (opcode & 0xFF) << 2; + const address = cpu.r[13] + offset; + + if (L) { + const value = bus.read32(address & 0xFFFF_FFFC); + cpu.r[rd] = std.math.rotr(u32, value, 8 * (address & 0x3)); + } else { + bus.write32(address & 0xFFFF_FFFC, cpu.r[rd]); + } + } + }.inner; +}