From 4ed4f8e1435e20f88865aaa01d0724ad48be8f5f Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Sun, 20 Nov 2022 17:42:46 -0400
Subject: [PATCH] fix(dma): implement obscure behaviour for DMAs from ROM

---
 src/core/bus/dma.zig | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/core/bus/dma.zig b/src/core/bus/dma.zig
index 6207d79..e00e623 100644
--- a/src/core/bus/dma.zig
+++ b/src/core/bus/dma.zig
@@ -256,11 +256,16 @@ fn DmaController(comptime id: u2) type {
                 cpu.bus.write(u16, dad_addr, @truncate(u16, rotr(u32, self.data_latch, 8 * (dad_addr & 3))));
             }
 
-            switch (sad_adj) {
-                .Increment => self.sad_latch +%= offset,
-                .Decrement => self.sad_latch -%= offset,
-                .IncrementReload => log.err("{} is a prohibited adjustment on SAD", .{sad_adj}),
-                .Fixed => {},
+            switch (@truncate(u8, sad_addr >> 24)) {
+                // according to fleroviux, DMAs with a source address in ROM misbehave
+                // the resultant behaviour is that the source address will increment despite what DMAXCNT says
+                0x08...0x0D => self.sad_latch +%= offset, // obscure behaviour
+                else => switch (sad_adj) {
+                    .Increment => self.sad_latch +%= offset,
+                    .Decrement => self.sad_latch -%= offset,
+                    .IncrementReload => log.err("{} is a prohibited adjustment on SAD", .{sad_adj}),
+                    .Fixed => {},
+                },
             }
 
             switch (dad_adj) {