From 472457b9f3ed9ddfe9c0734d7df196dd6ae3cc43 Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Mon, 31 Oct 2022 03:22:08 -0300
Subject: [PATCH] chore: make use of comptime control flow when working with
 tuples

---
 src/core/bus/dma.zig   |  8 ++++----
 src/core/bus/timer.zig | 20 ++++++++------------
 src/core/cpu.zig       | 29 ++++++-----------------------
 src/core/scheduler.zig |  5 +----
 4 files changed, 19 insertions(+), 43 deletions(-)

diff --git a/src/core/bus/dma.zig b/src/core/bus/dma.zig
index 63952e8..0856041 100644
--- a/src/core/bus/dma.zig
+++ b/src/core/bus/dma.zig
@@ -335,10 +335,10 @@ fn DmaController(comptime id: u2) type {
 }
 
 pub fn pollDmaOnBlank(bus: *Bus, comptime kind: DmaKind) void {
-    bus.dma[0].poll(kind);
-    bus.dma[1].poll(kind);
-    bus.dma[2].poll(kind);
-    bus.dma[3].poll(kind);
+    comptime var i: usize = 0;
+    inline while (i < 4) : (i += 1) {
+        bus.dma[i].poll(kind);
+    }
 }
 
 const Adjustment = enum(u2) {
diff --git a/src/core/bus/timer.zig b/src/core/bus/timer.zig
index 7167627..efa107a 100644
--- a/src/core/bus/timer.zig
+++ b/src/core/bus/timer.zig
@@ -190,19 +190,15 @@ fn Timer(comptime id: u2) type {
 
             // Perform Cascade Behaviour
             switch (id) {
-                0 => if (cpu.bus.tim[1].cnt.cascade.read()) {
-                    cpu.bus.tim[1]._counter +%= 1;
-                    if (cpu.bus.tim[1]._counter == 0) cpu.bus.tim[1].onTimerExpire(cpu, late);
+                inline 0, 1, 2 => |idx| {
+                    const next = idx + 1;
+
+                    if (cpu.bus.tim[next].cnt.cascade.read()) {
+                        cpu.bus.tim[next]._counter +%= 1;
+                        if (cpu.bus.tim[next]._counter == 0) cpu.bus.tim[next].onTimerExpire(cpu, late);
+                    }
                 },
-                1 => if (cpu.bus.tim[2].cnt.cascade.read()) {
-                    cpu.bus.tim[2]._counter +%= 1;
-                    if (cpu.bus.tim[2]._counter == 0) cpu.bus.tim[2].onTimerExpire(cpu, late);
-                },
-                2 => if (cpu.bus.tim[3].cnt.cascade.read()) {
-                    cpu.bus.tim[3]._counter +%= 1;
-                    if (cpu.bus.tim[3]._counter == 0) cpu.bus.tim[3].onTimerExpire(cpu, late);
-                },
-                3 => {}, // There is no Timer for TIM3 to "cascade" to,
+                3 => {}, // THere is no timer for TIM3 to cascade to
             }
 
             // Reschedule Timer if we're not cascading
diff --git a/src/core/cpu.zig b/src/core/cpu.zig
index 539547e..c634d6b 100644
--- a/src/core/cpu.zig
+++ b/src/core/cpu.zig
@@ -455,29 +455,12 @@ pub const Arm7tdmi = struct {
     }
 
     pub fn stepDmaTransfer(self: *Self) bool {
-        const dma0 = &self.bus.dma[0];
-        const dma1 = &self.bus.dma[1];
-        const dma2 = &self.bus.dma[2];
-        const dma3 = &self.bus.dma[3];
-
-        if (dma0.in_progress) {
-            dma0.step(self);
-            return true;
-        }
-
-        if (dma1.in_progress) {
-            dma1.step(self);
-            return true;
-        }
-
-        if (dma2.in_progress) {
-            dma2.step(self);
-            return true;
-        }
-
-        if (dma3.in_progress) {
-            dma3.step(self);
-            return true;
+        comptime var i: usize = 0;
+        inline while (i < 4) : (i += 1) {
+            if (self.bus.dma[i].in_progress) {
+                self.bus.dma[i].step(self);
+                return true;
+            }
         }
 
         return false;
diff --git a/src/core/scheduler.zig b/src/core/scheduler.zig
index 57b847b..e87dadc 100644
--- a/src/core/scheduler.zig
+++ b/src/core/scheduler.zig
@@ -46,10 +46,7 @@ pub const Scheduler = struct {
                 },
                 .TimerOverflow => |id| {
                     switch (id) {
-                        0 => cpu.bus.tim[0].onTimerExpire(cpu, late),
-                        1 => cpu.bus.tim[1].onTimerExpire(cpu, late),
-                        2 => cpu.bus.tim[2].onTimerExpire(cpu, late),
-                        3 => cpu.bus.tim[3].onTimerExpire(cpu, late),
+                        inline 0...3 => |idx| cpu.bus.tim[idx].onTimerExpire(cpu, late),
                     }
                 },
                 .ApuChannel => |id| {