From 1acc5e35e9e6eae34fa84475d0d782cd215917ca Mon Sep 17 00:00:00 2001 From: Rekai Musuka Date: Fri, 21 Oct 2022 05:13:02 -0300 Subject: [PATCH] chore: move util.zig --- src/core/Bus.zig | 4 ++-- src/core/apu.zig | 4 ++-- src/core/bus/backup.zig | 4 ++-- src/core/bus/dma.zig | 2 +- src/core/bus/io.zig | 2 +- src/core/bus/timer.zig | 2 +- src/core/cpu.zig | 8 ++++---- src/core/cpu/arm/branch.zig | 2 +- src/core/cpu/arm/half_signed_data_transfer.zig | 4 ++-- src/core/cpu/arm/psr_transfer.zig | 2 +- src/core/cpu/arm/single_data_swap.zig | 2 +- src/core/cpu/arm/single_data_transfer.zig | 4 ++-- src/core/cpu/barrel_shifter.zig | 2 +- src/core/cpu/thumb/branch.zig | 2 +- src/core/cpu/thumb/data_transfer.zig | 5 ++--- src/core/emu.zig | 4 ++-- src/main.zig | 2 +- src/platform.zig | 4 ++-- src/{core => }/util.zig | 4 ++-- 19 files changed, 31 insertions(+), 32 deletions(-) rename src/{core => }/util.zig (98%) diff --git a/src/core/Bus.zig b/src/core/Bus.zig index 893b9bf..56b00de 100644 --- a/src/core/Bus.zig +++ b/src/core/Bus.zig @@ -12,7 +12,7 @@ const Apu = @import("apu.zig").Apu; const DmaTuple = @import("bus/dma.zig").DmaTuple; const TimerTuple = @import("bus/timer.zig").TimerTuple; const Scheduler = @import("scheduler.zig").Scheduler; -const FilePaths = @import("util.zig").FilePaths; +const FilePaths = @import("../util.zig").FilePaths; const io = @import("bus/io.zig"); const Allocator = std.mem.Allocator; @@ -20,7 +20,7 @@ const log = std.log.scoped(.Bus); const createDmaTuple = @import("bus/dma.zig").create; const createTimerTuple = @import("bus/timer.zig").create; -const rotr = @import("util.zig").rotr; +const rotr = @import("../util.zig").rotr; const timings: [2][0x10]u8 = [_][0x10]u8{ // BIOS, Unused, EWRAM, IWRAM, I/0, PALRAM, VRAM, OAM, ROM0, ROM0, ROM1, ROM1, ROM2, ROM2, SRAM, Unused diff --git a/src/core/apu.zig b/src/core/apu.zig index 3c7e870..45aa03d 100644 --- a/src/core/apu.zig +++ b/src/core/apu.zig @@ -1,7 +1,7 @@ const std = @import("std"); const SDL = @import("sdl2"); const io = @import("bus/io.zig"); -const util = @import("util.zig"); +const util = @import("../util.zig"); const Arm7tdmi = @import("cpu.zig").Arm7tdmi; const Scheduler = @import("scheduler.zig").Scheduler; @@ -9,7 +9,7 @@ const Scheduler = @import("scheduler.zig").Scheduler; const SoundFifo = std.fifo.LinearFifo(u8, .{ .Static = 0x20 }); const AudioDeviceId = SDL.SDL_AudioDeviceID; -const intToBytes = @import("util.zig").intToBytes; +const intToBytes = @import("../util.zig").intToBytes; const log = std.log.scoped(.APU); pub const host_sample_rate = 1 << 15; diff --git a/src/core/bus/backup.zig b/src/core/bus/backup.zig index 123bb01..48cb603 100644 --- a/src/core/bus/backup.zig +++ b/src/core/bus/backup.zig @@ -2,8 +2,8 @@ const std = @import("std"); const Allocator = std.mem.Allocator; const log = std.log.scoped(.Backup); -const escape = @import("../util.zig").escape; -const span = @import("../util.zig").span; +const escape = @import("../../util.zig").escape; +const span = @import("../../util.zig").span; const backup_kinds = [6]Needle{ .{ .str = "EEPROM_V", .kind = .Eeprom }, diff --git a/src/core/bus/dma.zig b/src/core/bus/dma.zig index 428b478..719287b 100644 --- a/src/core/bus/dma.zig +++ b/src/core/bus/dma.zig @@ -1,5 +1,5 @@ const std = @import("std"); -const util = @import("../util.zig"); +const util = @import("../../util.zig"); const DmaControl = @import("io.zig").DmaControl; const Bus = @import("../Bus.zig"); diff --git a/src/core/bus/io.zig b/src/core/bus/io.zig index f4f2373..e6f4850 100644 --- a/src/core/bus/io.zig +++ b/src/core/bus/io.zig @@ -3,7 +3,7 @@ const builtin = @import("builtin"); const timer = @import("timer.zig"); const dma = @import("dma.zig"); const apu = @import("../apu.zig"); -const util = @import("../util.zig"); +const util = @import("../../util.zig"); const Bit = @import("bitfield").Bit; const Bitfield = @import("bitfield").Bitfield; diff --git a/src/core/bus/timer.zig b/src/core/bus/timer.zig index 77d82fe..f93ee36 100644 --- a/src/core/bus/timer.zig +++ b/src/core/bus/timer.zig @@ -1,5 +1,5 @@ const std = @import("std"); -const util = @import("../util.zig"); +const util = @import("../../util.zig"); const TimerControl = @import("io.zig").TimerControl; const Io = @import("io.zig").Io; diff --git a/src/core/cpu.zig b/src/core/cpu.zig index 9b579f1..3154be2 100644 --- a/src/core/cpu.zig +++ b/src/core/cpu.zig @@ -1,12 +1,12 @@ const std = @import("std"); -const util = @import("util.zig"); +const util = @import("../util.zig"); const Bus = @import("Bus.zig"); const Bit = @import("bitfield").Bit; const Bitfield = @import("bitfield").Bitfield; const Scheduler = @import("scheduler.zig").Scheduler; -const FilePaths = @import("util.zig").FilePaths; -const Logger = @import("util.zig").Logger; +const FilePaths = @import("../util.zig").FilePaths; +const Logger = @import("../util.zig").Logger; const File = std.fs.File; @@ -125,7 +125,7 @@ pub const thumb = struct { const swi = @import("cpu/thumb/software_interrupt.zig").fmt17; const branch = @import("cpu/thumb/branch.zig"); - /// Determine index into THUMB InstrFn LUT + /// Determine index into THUMB InstrFn LUT fn idx(opcode: u16) u10 { return @truncate(u10, opcode >> 6); } diff --git a/src/core/cpu/arm/branch.zig b/src/core/cpu/arm/branch.zig index 31a48f0..6015eb3 100644 --- a/src/core/cpu/arm/branch.zig +++ b/src/core/cpu/arm/branch.zig @@ -4,7 +4,7 @@ const Bus = @import("../../Bus.zig"); const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const InstrFn = @import("../../cpu.zig").arm.InstrFn; -const sext = @import("../../util.zig").sext; +const sext = @import("../../../util.zig").sext; pub fn branch(comptime L: bool) InstrFn { return struct { diff --git a/src/core/cpu/arm/half_signed_data_transfer.zig b/src/core/cpu/arm/half_signed_data_transfer.zig index d0a4b1d..d681da0 100644 --- a/src/core/cpu/arm/half_signed_data_transfer.zig +++ b/src/core/cpu/arm/half_signed_data_transfer.zig @@ -4,8 +4,8 @@ const Bus = @import("../../Bus.zig"); const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const InstrFn = @import("../../cpu.zig").arm.InstrFn; -const sext = @import("../../util.zig").sext; -const rotr = @import("../../util.zig").rotr; +const sext = @import("../../../util.zig").sext; +const rotr = @import("../../../util.zig").rotr; pub fn halfAndSignedDataTransfer(comptime P: bool, comptime U: bool, comptime I: bool, comptime W: bool, comptime L: bool) InstrFn { return struct { diff --git a/src/core/cpu/arm/psr_transfer.zig b/src/core/cpu/arm/psr_transfer.zig index b469083..3ee8791 100644 --- a/src/core/cpu/arm/psr_transfer.zig +++ b/src/core/cpu/arm/psr_transfer.zig @@ -7,7 +7,7 @@ const PSR = @import("../../cpu.zig").PSR; const log = std.log.scoped(.PsrTransfer); -const rotr = @import("../../util.zig").rotr; +const rotr = @import("../../../util.zig").rotr; pub fn psrTransfer(comptime I: bool, comptime R: bool, comptime kind: u2) InstrFn { return struct { diff --git a/src/core/cpu/arm/single_data_swap.zig b/src/core/cpu/arm/single_data_swap.zig index f0ccfef..63001f2 100644 --- a/src/core/cpu/arm/single_data_swap.zig +++ b/src/core/cpu/arm/single_data_swap.zig @@ -4,7 +4,7 @@ const Bus = @import("../../Bus.zig"); const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const InstrFn = @import("../../cpu.zig").arm.InstrFn; -const rotr = @import("../../util.zig").rotr; +const rotr = @import("../../../util.zig").rotr; pub fn singleDataSwap(comptime B: bool) InstrFn { return struct { diff --git a/src/core/cpu/arm/single_data_transfer.zig b/src/core/cpu/arm/single_data_transfer.zig index 794e610..3a82b0c 100644 --- a/src/core/cpu/arm/single_data_transfer.zig +++ b/src/core/cpu/arm/single_data_transfer.zig @@ -1,12 +1,12 @@ const std = @import("std"); -const util = @import("../../util.zig"); +const util = @import("../../../util.zig"); const shifter = @import("../barrel_shifter.zig"); const Bus = @import("../../Bus.zig"); const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const InstrFn = @import("../../cpu.zig").arm.InstrFn; -const rotr = @import("../../util.zig").rotr; +const rotr = @import("../../../util.zig").rotr; pub fn singleDataTransfer(comptime I: bool, comptime P: bool, comptime U: bool, comptime B: bool, comptime W: bool, comptime L: bool) InstrFn { return struct { diff --git a/src/core/cpu/barrel_shifter.zig b/src/core/cpu/barrel_shifter.zig index 7b2c1b8..32afff0 100644 --- a/src/core/cpu/barrel_shifter.zig +++ b/src/core/cpu/barrel_shifter.zig @@ -3,7 +3,7 @@ const std = @import("std"); const Arm7tdmi = @import("../cpu.zig").Arm7tdmi; const CPSR = @import("../cpu.zig").PSR; -const rotr = @import("../util.zig").rotr; +const rotr = @import("../../util.zig").rotr; pub fn execute(comptime S: bool, cpu: *Arm7tdmi, opcode: u32) u32 { var result: u32 = undefined; diff --git a/src/core/cpu/thumb/branch.zig b/src/core/cpu/thumb/branch.zig index 015137a..3425f3c 100644 --- a/src/core/cpu/thumb/branch.zig +++ b/src/core/cpu/thumb/branch.zig @@ -3,7 +3,7 @@ const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const InstrFn = @import("../../cpu.zig").thumb.InstrFn; const checkCond = @import("../../cpu.zig").checkCond; -const sext = @import("../../util.zig").sext; +const sext = @import("../../../util.zig").sext; pub fn fmt16(comptime cond: u4) InstrFn { return struct { diff --git a/src/core/cpu/thumb/data_transfer.zig b/src/core/cpu/thumb/data_transfer.zig index 481e3e5..8dda707 100644 --- a/src/core/cpu/thumb/data_transfer.zig +++ b/src/core/cpu/thumb/data_transfer.zig @@ -4,7 +4,8 @@ const Bus = @import("../../Bus.zig"); const Arm7tdmi = @import("../../cpu.zig").Arm7tdmi; const InstrFn = @import("../../cpu.zig").thumb.InstrFn; -const rotr = @import("../../util.zig").rotr; +const rotr = @import("../../../util.zig").rotr; +const sext = @import("../../../util.zig").sext; pub fn fmt6(comptime rd: u3) InstrFn { return struct { @@ -16,8 +17,6 @@ pub fn fmt6(comptime rd: u3) InstrFn { }.inner; } -const sext = @import("../../util.zig").sext; - pub fn fmt78(comptime op: u2, comptime T: bool) InstrFn { return struct { fn inner(cpu: *Arm7tdmi, bus: *Bus, opcode: u16) void { diff --git a/src/core/emu.zig b/src/core/emu.zig index ff18d9f..81ca1fc 100644 --- a/src/core/emu.zig +++ b/src/core/emu.zig @@ -4,8 +4,8 @@ const SDL = @import("sdl2"); const Bus = @import("Bus.zig"); const Scheduler = @import("scheduler.zig").Scheduler; const Arm7tdmi = @import("cpu.zig").Arm7tdmi; -const FpsTracker = @import("util.zig").FpsTracker; -const FilePaths = @import("util.zig").FilePaths; +const FpsTracker = @import("../util.zig").FpsTracker; +const FilePaths = @import("../util.zig").FilePaths; const Timer = std.time.Timer; const Thread = std.Thread; diff --git a/src/main.zig b/src/main.zig index 2b69c24..fd6cfeb 100644 --- a/src/main.zig +++ b/src/main.zig @@ -8,7 +8,7 @@ const Gui = @import("platform.zig").Gui; const Bus = @import("core/Bus.zig"); const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi; const Scheduler = @import("core/scheduler.zig").Scheduler; -const FilePaths = @import("core/util.zig").FilePaths; +const FilePaths = @import("util.zig").FilePaths; const Allocator = std.mem.Allocator; const log = std.log.scoped(.Cli); diff --git a/src/platform.zig b/src/platform.zig index 89d1640..319aea3 100644 --- a/src/platform.zig +++ b/src/platform.zig @@ -5,9 +5,9 @@ const emu = @import("core/emu.zig"); const Apu = @import("core/apu.zig").Apu; const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi; const Scheduler = @import("core/scheduler.zig").Scheduler; -const FpsTracker = @import("core/util.zig").FpsTracker; +const FpsTracker = @import("util.zig").FpsTracker; -const span = @import("core/util.zig").span; +const span = @import("util.zig").span; const pitch = @import("core/ppu.zig").framebuf_pitch; const scale = @import("core/emu.zig").win_scale; diff --git a/src/core/util.zig b/src/util.zig similarity index 98% rename from src/core/util.zig rename to src/util.zig index 51d2760..57896e8 100644 --- a/src/core/util.zig +++ b/src/util.zig @@ -1,9 +1,9 @@ const std = @import("std"); const builtin = @import("builtin"); const Log2Int = std.math.Log2Int; -const Arm7tdmi = @import("cpu.zig").Arm7tdmi; +const Arm7tdmi = @import("core/cpu.zig").Arm7tdmi; -const allow_unhandled_io = @import("emu.zig").allow_unhandled_io; +const allow_unhandled_io = @import("core/emu.zig").allow_unhandled_io; // Sign-Extend value of type `T` to type `U` pub fn sext(comptime T: type, comptime U: type, value: T) T {