From 1a23073424b77ee520eb52effa5acaf73094fda3 Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Fri, 21 Oct 2022 05:12:39 -0300
Subject: [PATCH] fix: incorrect order-of-operations in ARM BL impl

---
 src/cpu.zig            | 7 ++++---
 src/cpu/arm/branch.zig | 2 +-
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/cpu.zig b/src/cpu.zig
index 5ec9559..432c646 100644
--- a/src/cpu.zig
+++ b/src/cpu.zig
@@ -418,9 +418,10 @@ pub const Arm7tdmi = struct {
         if (self.cpsr.t.read()) {
             if (opcode >> 11 == 0x1E) {
                 // Instruction 1 of a BL Opcode, print in ARM mode
-                const tmp_opcode = self.bus.read(u32, self.r[15] - 2);
-                const be_opcode = tmp_opcode << 16 | tmp_opcode >> 16;
-                log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, be_opcode });
+                const other_half = self.bus.debugRead(u16, self.r[15]);
+                const bl_opcode = @as(u32, opcode) << 16 | other_half;
+
+                log_str = try std.fmt.bufPrint(&buf, arm_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, bl_opcode });
             } else {
                 log_str = try std.fmt.bufPrint(&buf, thumb_fmt, .{ r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, c_psr, opcode });
             }
diff --git a/src/cpu/arm/branch.zig b/src/cpu/arm/branch.zig
index 362366a..03b4fd5 100644
--- a/src/cpu/arm/branch.zig
+++ b/src/cpu/arm/branch.zig
@@ -10,7 +10,7 @@ pub fn branch(comptime L: bool) InstrFn {
     return struct {
         fn inner(cpu: *Arm7tdmi, _: *Bus, opcode: u32) void {
             if (L) cpu.r[14] = cpu.r[15];
-            cpu.r[15] = cpu.fakePC() +% sext(24, opcode << 2);
+            cpu.r[15] = cpu.fakePC() +% (sext(24, opcode) << 2);
         }
     }.inner;
 }