diff --git a/src/core/nds7/Bus.zig b/src/core/nds7/Bus.zig
index 0598322..859ad8d 100644
--- a/src/core/nds7/Bus.zig
+++ b/src/core/nds7/Bus.zig
@@ -78,7 +78,8 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
         0x0380_0000...0x03FF_FFFF => readInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count]),
         0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
         0x0600_0000...0x06FF_FFFF => self.vram.read(T, .nds7, aligned_addr),
-        else => warn("unexpected read: 0x{x:0>8} -> {}", .{ aligned_addr, T }),
+
+        else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
     };
 }
 
@@ -112,7 +113,7 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
         0x0380_0000...0x0380_FFFF => writeInt(T, self.wram[aligned_addr & 0x0000_FFFF ..][0..byte_count], value),
         0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
         0x0600_0000...0x06FF_FFFF => self.vram.write(T, .nds7, aligned_addr, value),
-        else => log.warn("unexpected write: 0x{X:}{} -> 0x{X:0>8}", .{ value, T, aligned_addr }),
+        else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
     }
 }
 
diff --git a/src/core/nds7/io.zig b/src/core/nds7/io.zig
index c5b126e..9ff7367 100644
--- a/src/core/nds7/io.zig
+++ b/src/core/nds7/io.zig
@@ -113,7 +113,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
 
             0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds7, value),
             0x0400_0184 => bus.io.shr.ipc.setIpcFifoCnt(.nds7, value),
-            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>4})", .{ T, address, value }),
         },
         u8 => switch (address) {
             // DMA Transfers
@@ -123,7 +123,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
             0x0400_0100...0x0400_010F => log.warn("TODO: Implement Timer", .{}),
 
             0x0400_0208 => bus.io.ime = value & 1 == 1,
-            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>2})", .{ T, address, value }),
         },
         else => @compileError(T ++ " is an unsupported bus write type"),
     }
diff --git a/src/core/nds9/Bus.zig b/src/core/nds9/Bus.zig
index 7611197..2410a92 100644
--- a/src/core/nds9/Bus.zig
+++ b/src/core/nds9/Bus.zig
@@ -74,7 +74,7 @@ fn _read(self: *@This(), comptime T: type, comptime mode: Mode, address: u32) T
         0x0400_0000...0x04FF_FFFF => io.read(self, T, aligned_addr),
         0x0600_0000...0x06FF_FFFF => self.ppu.vram.read(T, .nds9, aligned_addr),
         0xFFFF_0000...0xFFFF_FFFF => self.bios.read(T, address),
-        else => warn("unexpected read: 0x{x:0>8} -> {}", .{ aligned_addr, T }),
+        else => warn("unexpected: read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }),
     };
 }
 
@@ -104,7 +104,7 @@ fn _write(self: *@This(), comptime T: type, comptime mode: Mode, address: u32, v
         0x0400_0000...0x04FF_FFFF => io.write(self, T, aligned_addr, value),
         0x0600_0000...0x06FF_FFFF => self.ppu.vram.write(T, .nds9, aligned_addr, value),
         0xFFFF_0000...0xFFFF_FFFF => self.bios.write(T, address, value),
-        else => log.warn("unexpected write: 0x{X:}{} -> 0x{X:0>8}", .{ value, T, aligned_addr }),
+        else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
     }
 }
 
diff --git a/src/core/nds9/io.zig b/src/core/nds9/io.zig
index 83cc677..a9f7651 100644
--- a/src/core/nds9/io.zig
+++ b/src/core/nds9/io.zig
@@ -144,7 +144,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
 
             0x0400_0304 => bus.io.powcnt.raw = value,
 
-            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>4})", .{ T, address, value }),
         },
         u8 => switch (address) {
             0x0400_0240 => {
@@ -188,7 +188,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void {
                 bus.ppu.vram.update();
             },
 
-            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }),
+            else => log.warn("unexpected: write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>2})", .{ T, address, value }),
         },
         else => @compileError(T ++ " is an unsupported bus write type"),
     }