From 422e0d00b8f5ee39d4ddb134936423ed876f2191 Mon Sep 17 00:00:00 2001 From: paoda Date: Wed, 14 Feb 2024 13:51:06 -0600 Subject: [PATCH] chore: improve debug messages --- .gitignore | 2 ++ src/core/nds7/dma.zig | 29 ++++++++++++++++++++++++++++- src/core/nds7/io.zig | 16 ++++++++-------- src/core/nds9/dma.zig | 31 +++++++++++++++++++++++++++++-- src/core/nds9/io.zig | 12 ++++++------ 5 files changed, 73 insertions(+), 17 deletions(-) diff --git a/.gitignore b/.gitignore index 7429489..dff9577 100644 --- a/.gitignore +++ b/.gitignore @@ -4,3 +4,5 @@ bin/ doc/ imgui.ini .build_config/ + +**/*.log diff --git a/src/core/nds7/dma.zig b/src/core/nds7/dma.zig index e9e785c..880887a 100644 --- a/src/core/nds7/dma.zig +++ b/src/core/nds7/dma.zig @@ -223,7 +223,34 @@ fn Controller(comptime id: u2) type { else => log.err("TODO: Implement DMA({}) {s} mode", .{ id, @tagName(start_timing) }), } - log.debug("configured {s} transfer from 0x{X:0>8} -> 0x{X:0>8} ({} words) for DMA{}", .{ @tagName(start_timing), self.sad_latch, self.dad_latch, self._word_count, id }); + // Debug stuff + { + const sad_adj: Adjustment = @enumFromInt(new.sad_adj.read()); + const dad_adj: Adjustment = @enumFromInt(new.dad_adj.read()); + const byte_count = @as(u32, @sizeOf(u16)) << @intFromBool(new.transfer_type.read()); + + const sad_final = switch (sad_adj) { + .Increment, .IncrementReload => self.sad_latch +% self._word_count * byte_count, + .Decrement => self.sad_latch -% self._word_count * byte_count, + .Fixed => self.sad_latch, + }; + + const dad_final = switch (dad_adj) { + .Increment, .IncrementReload => self.dad_latch +% self._word_count * byte_count, + .Decrement => self.dad_latch -% self._word_count * byte_count, + .Fixed => self.dad_latch, + }; + + log.debug("configured {s} transfer from 0x{X:0>8} -> 0x{X:0>8} to 0x{X:0>8} -> 0x{X:0>8} ({} words) for DMA{}", .{ + @tagName(start_timing), + self.sad_latch, + sad_final, + self.dad_latch, + dad_final, + self._word_count, + id, + }); + } } self.cnt.raw = halfword; diff --git a/src/core/nds7/io.zig b/src/core/nds7/io.zig index 1b21810..0271f2c 100644 --- a/src/core/nds7/io.zig +++ b/src/core/nds7/io.zig @@ -57,7 +57,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T { 0x0400_00B0...0x0400_00DC => dma.read(T, &bus.dma, address) orelse 0x000_0000, // Timers - 0x0400_0100...0x0400_010C => warn("TODO: impl timer", .{}), + 0x0400_0100...0x0400_010C => warn("TODO(timer): read(T: {}, addr: 0x{X:0>8}) {}", .{ T, address, T }), 0x0400_0180 => bus.io.shr.ipc._nds7.sync.raw, 0x0400_0208 => @intFromBool(bus.io.ime), @@ -73,7 +73,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T { 0x0400_00B0...0x0400_00DE => dma.read(T, &bus.dma, address) orelse 0x0000, // Timers - 0x0400_0100...0x0400_010E => warn("TODO: impl timer", .{}), + 0x0400_0100...0x0400_010E => warn("TODO(timer): read(T: {}, addr: 0x{X:0>8}) {}", .{ T, address, T }), 0x0400_0130 => bus.io.shr.input.keyinput().raw, 0x0400_0136 => bus.io.shr.input.extkeyin().raw, @@ -87,10 +87,10 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T { 0x0400_00B0...0x0400_00DF => dma.read(T, &bus.dma, address) orelse 0x00, // Timers - 0x0400_0100...0x0400_010F => warn("TODO: impl timer", .{}), + 0x0400_0100...0x0400_010F => warn("TODO(timer): read(T: {}, addr: 0x{X:0>8}) {}", .{ T, address, T }), // RTC - 0x0400_0138 => warn("TODO: RTC read", .{}), + 0x0400_0138 => warn("TODO(rtc): read(T: {}, addr: 0x{X:0>8}) {}", .{ T, address, T }), 0x0400_0240 => bus.vram.stat().raw, 0x0400_0241 => bus.io.shr.wramcnt.raw, @@ -109,7 +109,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void { 0x0400_00B0...0x0400_00DC => dma.write(T, &bus.dma, address, value), // Timers - 0x0400_0100...0x0400_010C => log.warn("TODO: impl timer", .{}), + 0x0400_0100...0x0400_010C => log.warn("TODO(timer): write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }), 0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds7, value), 0x0400_0208 => bus.io.ime = value & 1 == 1, @@ -126,7 +126,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void { 0x0400_00B0...0x0400_00DE => dma.write(T, &bus.dma, address, value), // Timers - 0x0400_0100...0x0400_010E => log.warn("TODO: impl timer", .{}), + 0x0400_0100...0x0400_010E => log.warn("TODO(timer): write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }), 0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds7, value), 0x0400_0184 => bus.io.shr.ipc.setIpcFifoCnt(.nds7, value), @@ -139,10 +139,10 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void { 0x0400_00B0...0x0400_00DF => dma.write(T, &bus.dma, address, value), // Timers - 0x0400_0100...0x0400_010F => log.warn("TODO: impl timer", .{}), + 0x0400_0100...0x0400_010F => log.warn("TODO(timer): write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }), // RTC - 0x0400_0138 => log.warn("TODO: RTC write", .{}), + 0x0400_0138 => log.warn("TODO(rtc): write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }), 0x0400_0208 => bus.io.ime = value & 1 == 1, diff --git a/src/core/nds9/dma.zig b/src/core/nds9/dma.zig index fb1ab39..6a445ce 100644 --- a/src/core/nds9/dma.zig +++ b/src/core/nds9/dma.zig @@ -223,7 +223,34 @@ fn Controller(comptime id: u2) type { else => log.err("TODO: Implement DMA({}) {s} mode", .{ id, @tagName(start_timing) }), } - log.debug("configured {s} transfer from 0x{X:0>8} -> 0x{X:0>8} ({} words) for DMA{}", .{ @tagName(start_timing), self.sad_latch, self.dad_latch, self._word_count, id }); + // Debug stuff + { + const sad_adj: Adjustment = @enumFromInt(new.sad_adj.read()); + const dad_adj: Adjustment = @enumFromInt(new.dad_adj.read()); + const byte_count = @as(u32, @sizeOf(u16)) << @intFromBool(new.transfer_type.read()); + + const sad_final = switch (sad_adj) { + .Increment, .IncrementReload => self.sad_latch +% self._word_count * byte_count, + .Decrement => self.sad_latch -% self._word_count * byte_count, + .Fixed => self.sad_latch, + }; + + const dad_final = switch (dad_adj) { + .Increment, .IncrementReload => self.dad_latch +% self._word_count * byte_count, + .Decrement => self.dad_latch -% self._word_count * byte_count, + .Fixed => self.dad_latch, + }; + + log.debug("configured {s} transfer from 0x{X:0>8} -> 0x{X:0>8} to 0x{X:0>8} -> 0x{X:0>8} ({} words) for DMA{}", .{ + @tagName(start_timing), + self.sad_latch, + sad_final, + self.dad_latch, + dad_final, + self._word_count, + id, + }); + } } self.cnt.raw = halfword; @@ -235,7 +262,7 @@ fn Controller(comptime id: u2) type { } pub fn step(self: *Self, cpu: *System.Arm946es) void { - const bus_ptr: *System.Bus7 = @ptrCast(@alignCast(cpu.bus.ptr)); + const bus_ptr: *System.Bus9 = @ptrCast(@alignCast(cpu.bus.ptr)); const is_fifo = (id == 1 or id == 2) and self.cnt.start_timing.read() == 0b11; const sad_adj: Adjustment = @enumFromInt(self.cnt.sad_adj.read()); diff --git a/src/core/nds9/io.zig b/src/core/nds9/io.zig index 9000ddc..9b7caa2 100644 --- a/src/core/nds9/io.zig +++ b/src/core/nds9/io.zig @@ -58,7 +58,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T { 0x0400_00E0...0x0400_00EC => std.mem.readInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], .little), // Timers - 0x0400_0100...0x0400_010C => warn("TODO: impl timer", .{}), + 0x0400_0100...0x0400_010C => warn("TODO(timer): read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }), 0x0400_0180 => bus.io.shr.ipc._nds9.sync.raw, 0x0400_0208 => @intFromBool(bus.io.ime), @@ -92,7 +92,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T { 0x0400_00E0...0x0400_00EE => std.mem.readInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], .little), // Timers - 0x0400_0100...0x0400_010E => warn("TODO: impl timer", .{}), + 0x0400_0100...0x0400_010E => warn("TODO(timer): read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }), 0x0400_0004 => bus.ppu.io.nds9.dispstat.raw, 0x0400_0130 => bus.io.shr.input.keyinput().raw, @@ -125,7 +125,7 @@ pub fn read(bus: *const Bus, comptime T: type, address: u32) T { 0x0400_00E0...0x0400_00EF => std.mem.readInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], .little), // Timers - 0x0400_0100...0x0400_010F => warn("TODO: impl timer", .{}), + 0x0400_0100...0x0400_010F => warn("TODO(timer): read(T: {}, addr: 0x{X:0>8}) {} ", .{ T, address, T }), 0x0400_0208 => @intFromBool(bus.io.ime), @@ -173,7 +173,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void { 0x0400_00E0...0x0400_00EC => std.mem.writeInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], value, .little), // Timers - 0x0400_0100...0x0400_010C => log.warn("TODO: impl timer", .{}), + 0x0400_0100...0x0400_010C => log.warn("TODO(timer): write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }), 0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds9, value), 0x0400_0184 => bus.io.shr.ipc.setIpcFifoCnt(.nds9, value), @@ -265,7 +265,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void { 0x0400_00E0...0x0400_00EE => std.mem.writeInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], value, .little), // Timers - 0x0400_0100...0x0400_010E => log.warn("TODO: impl timer", .{}), + 0x0400_0100...0x0400_010E => log.warn("TODO(timer): write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }), 0x0400_0180 => bus.io.shr.ipc.setIpcSync(.nds9, value), 0x0400_0184 => bus.io.shr.ipc.setIpcFifoCnt(.nds9, value), @@ -305,7 +305,7 @@ pub fn write(bus: *Bus, comptime T: type, address: u32, value: T) void { 0x0400_00E0...0x0400_00EF => std.mem.writeInt(T, bus.io.dma_fill[address & 0xF ..][0..@sizeOf(T)], value, .little), // Timers - 0x0400_0100...0x0400_010F => log.warn("TODO: impl timer", .{}), + 0x0400_0100...0x0400_010F => log.warn("TODO(timer): write(T: {}, addr: 0x{X:0>8}, value: 0x{X:0>8})", .{ T, address, value }), 0x0400_0208 => bus.io.ime = value & 1 == 1,