From 334cd432d438d4c03fd72688b0ef54e391c0a970 Mon Sep 17 00:00:00 2001 From: Rekai Musuka Date: Thu, 14 Dec 2023 21:14:58 -0600 Subject: [PATCH] tmp: some debug logs for dmas lol --- src/core/nds7/dma.zig | 10 ++++++++++ src/core/nds9/dma.zig | 10 ++++++++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/src/core/nds7/dma.zig b/src/core/nds7/dma.zig index 8226df0..e9e785c 100644 --- a/src/core/nds7/dma.zig +++ b/src/core/nds7/dma.zig @@ -214,6 +214,16 @@ fn Controller(comptime id: u2) type { // Only a Start Timing of 00 has a DMA Transfer immediately begin self.in_progress = new.start_timing.read() == 0b00; + + // this is just for debug purposes + const start_timing: Kind = @enumFromInt(new.start_timing.read()); + + switch (start_timing) { + .immediate, .vblank => {}, + else => log.err("TODO: Implement DMA({}) {s} mode", .{ id, @tagName(start_timing) }), + } + + log.debug("configured {s} transfer from 0x{X:0>8} -> 0x{X:0>8} ({} words) for DMA{}", .{ @tagName(start_timing), self.sad_latch, self.dad_latch, self._word_count, id }); } self.cnt.raw = halfword; diff --git a/src/core/nds9/dma.zig b/src/core/nds9/dma.zig index 6820bb1..6a281f2 100644 --- a/src/core/nds9/dma.zig +++ b/src/core/nds9/dma.zig @@ -215,9 +215,15 @@ fn Controller(comptime id: u2) type { // Only a Start Timing of 00 has a DMA Transfer immediately begin self.in_progress = new.start_timing.read() == 0b00; - if (self.in_progress) { - log.debug("Immediate DMA9({}): 0x{X:0>8} -> 0x{X:0>8} {} words", .{ id, self.sad_latch, self.dad_latch, self._word_count }); + // this is just for debug purposes + const start_timing: Kind = @enumFromInt(new.start_timing.read()); + + switch (start_timing) { + .immediate, .vblank => {}, + else => log.err("TODO: Implement DMA({}) {s} mode", .{ id, @tagName(start_timing) }), } + + log.debug("configured {s} transfer from 0x{X:0>8} -> 0x{X:0>8} ({} words) for DMA{}", .{ @tagName(start_timing), self.sad_latch, self.dad_latch, self._word_count, id }); } self.cnt.raw = halfword;