From b1bbd67832f69a0517995e4707569e712782722e Mon Sep 17 00:00:00 2001
From: Rekai Musuka <rekai@musuka.dev>
Date: Mon, 24 Aug 2020 00:53:47 -0500
Subject: [PATCH] Implement 2 opcodes

---
 src/instruction.rs | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/instruction.rs b/src/instruction.rs
index 935ae58..0ac782a 100644
--- a/src/instruction.rs
+++ b/src/instruction.rs
@@ -29,6 +29,7 @@ pub enum Instruction {
     XOR,
     OR,
     CP,
+    RET(Condition),
 }
 
 pub enum AllRegisters {
@@ -152,6 +153,19 @@ impl Instruction {
                 Self::arg_table_r(z),
             ),
             (2, z, _, y, _) => Self::table_alu(y, z),
+            (3, 0, _, 0..=3, _) => Instruction::RET(
+                // RET cc[y]
+                Self::table_cc(y),
+            ),
+            (3, 0, _, 4, _) => Instruction::LD(
+                // LD (0xFF00 + n), A
+                Argument::IndirectImmediateByte(0xFF00 + (n as u16)),
+                Argument::Register(Register::A),
+            ),
+            (3, 0, _, 5, _) => Instruction::ADD(
+                Argument::RegisterPair(RegisterPair::SP),
+                Argument::ImmediateByte(d),
+            ),
             _ => unreachable!(),
         }
     }